Stress-reduced field-effect semiconductor device and method for forming therefor

• US 8,907,408 B2
• Filed: 03/26/2012
• Issued: 12/09/2014
• Est. Priority Date: 03/26/2012
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Sedlmaier, Stefan, Zundel, Markus, Hirler, Franz, Baumgartl, Johannes, Mauder, Anton, Siemieniec, Ralf, Blank, Oliver, Hutzler, Michael
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US13/429,525
• Publication Number:
  US 20130248993A1
• Time in Patent Office: 988 Days
• Field of Search: 257/329
• US Class Current: 257/329
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body. The vertical trench includes a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. Further, a method for producing a field-effect semiconductor device is provided.

Claims

1. A field-effect semiconductor device, comprising a semiconductor body with a first surface defining a vertical direction, the field-effect semiconductor device further comprising in a vertical cross-section:

a vertical trench extending from the first surface into the semiconductor body and comprising a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode,

wherein the interface between the insulation structure and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress by generating a compressive stress.

2. The field-effect semiconductor device of claim 1, wherein the cavity has a vertical extension larger than about 20 nm.

3. The field-effect semiconductor device of claim 1, wherein the cavity has, in the vertical cross-section, a maximum horizontal extension and a maximum vertical extension larger than the maximum horizontal extension.

4. The field-effect semiconductor device of claim 1, wherein the vertical trench has a maximum vertical extension, and wherein the cavity has a maximum vertical extension larger than about a third of the maximum vertical extension of the vertical trench.

5. The field-effect semiconductor device of claim 1, wherein the cavity adjoins the field electrode.

6. The field-effect semiconductor device of claim 1, wherein the cavity is completely surrounded by the field electrode.

7. The field-effect semiconductor device of claim 1, wherein the cavity is, in the vertical cross-section, substantially centered with regard to a central vertical axis of the field electrode.

8. The field-effect semiconductor device of claim 1, wherein the insulation structure comprises different dielectric materials.

9. The field-effect semiconductor device of claim 1, wherein the cavity extends substantially parallel to the field electrode along a length of the trench sidewalls.

10. The field-effect semiconductor device of claim 1, wherein the cavity is unfilled.

11. The field-effect semiconductor device of claim 1, wherein the cavity is filled by any one of:

a resin, an imide and an aerogel.

12. A semiconductor device, comprising:

a semiconductor body comprising a first surface defining a vertical direction, a substantially vertically orientated outer edge, and an active area spaced apart from the outer edge, the active area comprising a plurality of insulated gate electrodes arranged next to the first surface and extending into the semiconductor body, and a plurality of dielectric regions spaced apart from the insulated gate electrodes and extending from the first surface into the semiconductor body and at least partially vertically below the insulated gate electrodes; and

at least one of a cavity arranged below the first surface and between the outer edge and the active area, a cavity arranged below the first surface and in a kerf region, a cavity arranged next to a lowermost portion of at least one of the plurality of dielectric regions, and a cavity comprising, in a vertical cross-section, a maximum horizontal extension and a maximum vertical extension larger than the maximum horizontal extension

wherein the interface between the dielectric regions and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress by generating a compressive stress.

13. The semiconductor device of claim 12, wherein a maximum distance of the dielectric regions to the first surface substantially matches a maximum distance of the cavity to the first surface.

14. The semiconductor device of claim 12, wherein the semiconductor device includes a plurality of cavities forming a lattice.

15. The semiconductor device of claim 12, wherein the semiconductor body comprises a source region, a drift region and a body region forming respective pn-junctions with the source region and the drift region, wherein each of the insulated gate electrodes is insulated from the semiconductor body by a gate dielectric region adjoining the source region, the body region and the drift region, and wherein each one of the plurality of dielectric regions extends into the semiconductor body at least along the drift region.

16. The field-effect semiconductor device of claim 12, wherein the cavity is at least partially filled with an elastic material.

17. A field-effect semiconductor device, comprising:

a semiconductor body comprising a first surface defining a vertical direction;

a trench gate electrode extending from the first surface into the semiconductor body and insulated from the semiconductor body by a gate dielectric region; and

a cavity arranged, in the vertical direction, at least partially below the trench gate electrode,

wherein the interface between the gate dielectric region and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress by generating a compressive stress.

18. The field-effect semiconductor device of claim 17, wherein the cavity has, in a vertical cross-section, a maximum horizontal extension larger than about 20 nm and a maximum vertical extension larger than the maximum horizontal extension.

19. The field-effect semiconductor device of claim 17, wherein the trench gate electrode, the gate dielectric region and the cavity are formed in a vertical trench comprising, in a vertical cross-section and in a vertical depth, a horizontal extension, and wherein the cavity comprises a horizontal extension which is at least about a fifth of the horizontal extension of the vertical trench.