Semiconductor device

• US 8,907,412 B2
• Filed: 09/16/2013
• Issued: 12/09/2014
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US14/028,017
• Publication Number:
  US 20140070308A1
• Time in Patent Office: 449 Days
• Field of Search: 257/330, 257/228, 257/229, 257/341
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Claims

1. A semiconductor device, comprising:

a first-conductivity-type source region overlying a second-conductivity-type body region;

a further second-conductivity-type region separating said second-conductivity-type body region from a first-conductivity-type drain region;

a first trench comprising a gate electrode which is capacitively connected to said second-conductivity-type body region through a gate oxide layer;

spatially fixed charges in an oxide layer in said trench, which are at a lower depth than said gate electrode, but which are not in at least some portions of said gate oxide layer;

wherein said spatially fixed charges have a polarity which tends to invert said further second-conductivity-type region adjacent to said first trench, at a lower depth than the bottom of said gate oxide;

wherein said spatially fixed charges are cesium ions.

2. The semiconductor device of claim 1, wherein said spatially fixed charges are at a depth which is at least the width of the gate electrode below said gate electrode.

3. The semiconductor device of claim 1, wherein said spatially fixed charges invert a portion of said further second-conductivity-type region under zero applied bias.

4. The semiconductor device of claim 1, wherein said semiconductor device comprises silicon.

5. The semiconductor device of claim 1, further comprising a second trench comprising spatially fixed charges.

6. The semiconductor device of claim 1, wherein said spatially fixed charges are intentionally introduced charges.

7. The semiconductor device of claim 1, wherein said spatially fixed charges at least partially balance the induced net charge in inverted regions of said further second-conductivity-type region, when said further second-conductivity-type region is inverted.

8. A semiconductor device, comprising:

a first-conductivity-type source region overlying a second-conductivity-type body region;

a further second-conductivity-type region separating said second-conductivity-type body region from a first-conductivity-type drain region;

a first trench comprising a gate electrode which is capacitively coupled to said second-conductivity-type body region through a gate oxide layer, and which is not substantially capacitively coupled to said gate electrode;

spatially fixed charges in an oxide layer in said first trench, which are at a lower depth than said gate electrode, but which are not in at least some portions of said gate oxide layer;

a second trench comprising spatially fixed charges;

wherein said spatially fixed charges are of a polarity which tends to invert said further second-conductivity-type region;

wherein said spatially fixed charges are cesium ions.

9. The semiconductor device of claim 8, wherein said spatially fixed charges invert a portion of said further second-conductivity-type region under zero applied bias.

10. The semiconductor device of claim 8, wherein said semiconductor device comprises silicon.

11. The semiconductor device of claim 8, wherein said spatially fixed charges are intentionally introduced charges.

12. The semiconductor device of claim 8, wherein said spatially fixed charges at least partially balance the induced net charge in inverted regions of said further second-conductivity-type region, when said further second-conductivity-type region is inverted.

13. A semiconductor device, comprising:

a first-conductivity-type source region overlying a second-conductivity-type body region;

a further second-conductivity-type region separating said second-conductivity-type body region from a first-conductivity-type drain region;

a trench comprising a gate electrode which is capacitively coupled to said second-conductivity-type body region through a gate oxide layer, and a thick bottom oxide layer;

spatially fixed charges in at least some of said thick bottom oxide layer, but not in at least some portions of said gate oxide layer;

wherein said spatially fixed charges have a polarity which tends to invert said further second-conductivity-type region;

wherein said spatially fixed charges invert at least some adjacent portions of said further second-conductivity-type region under zero applied bias; and

wherein said spatially fixed charges are cesium ions.

14. The semiconductor device of claim 13, wherein said semiconductor device comprises silicon.

15. The semiconductor device of claim 13, further comprising a second trench, wherein said second trench comprises spatially fixed charges.

16. The semiconductor device of claim 13, wherein said spatially fixed charges are intentionally introduced charges.

17. The semiconductor device of claim 13, wherein said spatially fixed charges at least partially balance the induced net charge in inverted regions of said further second-conductivity-type region, when said further second-conductivity-type region is inverted.