Dual gate oxide trench MOSFET with channel stop trench

• US 8,907,416 B2
• Filed: 02/28/2013
• Issued: 12/09/2014
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Lui, Sik, Wang, Xiaobin
• Primary Examiner(s): Jung, Michael
• Application Number:
  US13/780,579
• Publication Number:
  US 20130175612A1
• Time in Patent Office: 649 Days
• Field of Search: None
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Claims

1. A semiconductor device comprising:

a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate;

a first gate runner formed in a first gate runner trench in the semiconductor substrate and electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the active region;

a second gate runner formed in a second gate runner trench and connected to the first gate runner for making contact to a gate metal; and

wherein an insulator layer in the first and second gate runner trenches have respective thicknesses T2 greater than a thickness T1 of the gate insulator layer in the active trenches,

wherein the thicknesses T2 are thick enough to support a blocking voltage, wherein each active trench contains a single electrode electrically connected to a gate potential as a gate electrode, wherein the active trench is filled only with the single electrode and the gate insulator layer.

2. The device of claim 1 further comprising:

a termination structure that surrounds the first and second gate runners and the active region, wherein the termination structure includes a conductive material in an insulator-lined trench in the semiconductor substrate, wherein the termination structure is electrically shorted to a source or body layer of the semiconductor substrate near a die edge thereby forming a channel stop for the device.

3. The device of claim 2 wherein the insulator in said insulator-lined trench of the termination structure is thick enough to support the blocking voltage.

4. The device of claim 1 further comprising:

a dielectric filled trench that surrounds the first and second gate runners and the active region.

5. The device of claim 4 further comprising a highly doped channel stop region under the dielectric filled trench.

6. The device of claim 1 wherein the semiconductor substrate includes a body layer in the active region and a termination region.

7. The device of claim 6 wherein the semiconductor substrate includes a source region.

8. The device of claim 7 wherein the source region is located only in the active region.

9. The device of claim 1 wherein the first gate runner includes a channel stop region formed under the first gate runner trench.

10. The device of claim 1 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer, wherein the first gate runner trench is deep enough to reach the heavily doped bottom layer.

11. A semiconductor device comprising:

a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate;

a first gate runner formed in a first gate runner trench in the semiconductor substrate and electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the active region;

a second gate runner formed in a second gate runner trench and connected to the first gate runner for making contact to a gate metal; and

wherein an insulator layer in the first and second gate runner trenches have respective thicknesses T2 greater than a thickness T1 of the gate insulator layer in the active trenches,

wherein the thicknesses T2 are thick enough to support a blocking voltage, wherein the first or second gate runner trench contains a single gate runner electrically connected to a gate potential, wherein the gate runner trench is filled only with the single gate runner and the gate insulator layer.

12. The device of claim 11 further comprising:

a termination structure that surrounds the first and second gate runners and the active region, wherein the termination structure includes a conductive material in an insulator-lined trench in the semiconductor substrate, wherein the termination structure is electrically shorted to a source or body layer of the semiconductor substrate near a die edge thereby forming a channel stop for the device.

13. The device of claim 12 wherein the insulator in said insulator-lined trench of the termination structure is thick enough to support the blocking voltage.

14. The device of claim 11 further comprising:

a dielectric filled trench that surrounds the first and second gate runners and the active region.

15. The device of claim 14 further comprising a highly doped channel stop region under the dielectric filled trench.

16. The device of claim 11 wherein the semiconductor substrate includes a body layer in the active region and a termination region.

17. The device of claim 16 wherein the semiconductor substrate includes a source region.

18. The device of claim 17 wherein the source region is located only in the active region.

19. The device of claim 11 wherein the first gate runner includes a channel stop region formed under the first gate runner trench.

20. The device of claim 11 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer, wherein the first gate runner trench is deep enough to reach the heavily doped bottom layer.