High speed backside illuminated, front side contact photodiode array

• US 8,907,440 B2
• Filed: 07/31/2013
• Issued: 12/09/2014
• Est. Priority Date: 05/05/2003
• Status: Active Grant

• Current Assignee: OSI Optoelectronics, Inc. (OSI Systems Incorporated)
• Original Assignee: OSI Optoelectronics, Inc. (OSI Systems Incorporated)
• Inventors: Bui, Peter Steven, Taneja, Narayan Dass
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US13/955,299
• Publication Number:
  US 20140061843A1
• Time in Patent Office: 496 Days
• Field of Search: 257/233, 257290-292, 257/414, 257431-496, 257/110, 257/279, 257/509, 257/525, 257544-550, 257/656, 257/927, 257/929, 257E21008-E21021, 257/E21.364, 438/48, 438/54, 438/65, 438/69, 438/70, 438/171, 438/190, 438/210, 438238-253, 438/329, 438/379, 438/387, 438/444, 438/901
• US Class Current: 257/448
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/102 characterised by only one potential barrier
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

The present specification discloses front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise. The photodiode array is made of photodiodes with front metallic cathode pads, front metallic anode pad, back metallic cathode pads, n+ doped regions and a p+ doped region. The front metallic cathode pads physically contact the n+ doped regions and the front metallic anode pad physically contacts the p+ doped region. The back metallic cathode pads physically contact the n+ doped region.

Claims

1. A photodiode array having a front side and a back side separated by a layer of silicon and a top edge, a bottom edge, a right edge, and a left edge, comprising:

a plurality of metallic cathode pads extending from a surface of said front side of the photodiode array, wherein each of said metallic cathode pads is in physical contact with at least one n+ doped region and wherein said metallic cathode pads are interconnected by a metallic connections;

a plurality of metallic cathode pads extending from a surface of said back side of the photodiode array wherein each of said metallic cathode pads is in physical contact with a second n+ doped region and wherein said metallic cathode pads are interconnected by a metallic connections; and

an anode pad extending from the said front side of the photodiode array, wherein said anode pad is in physical contact with a p+ doped region.

2. The photodiode array of claim 1, wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising a first metallic cathode pad and a second metallic cathode pad extending from said front side of the photodiode array.

3. The photodiode array of claim 1, wherein said anode pad is positioned between a first metallic cathode pad and a second metallic cathode pad.

4. The photodiode array of claim 1, wherein the layer of silicon is in the range of 80 to 200 microns thick.

5. The photodiode array of claim 1, wherein the second n+ doped region is on the order of 0.3 micrometers.

6. The photodiode array of claim 1, wherein the second n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter.

7. The photodiode array of claim 1, wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm.

8. The photodiode array of claim 1, wherein said photodiode array has a rise time of 40 nanoseconds or less.

9. The photodiode array of claim 1, wherein said metallic connections on the front side of said array define a grid of at least 64 cells, each of said cells comprising a photodiode.

10. A photodiode array having a front side and a back side separated by a layer of silicon, comprising:

a plurality of metallic cathode pads extending from a surface of said front side of the photodiode array, wherein said metallic cathode pads are interconnected by a metallic connections;

a plurality of metallic cathode pads extending from a surface of said back side of the photodiode array, wherein said metallic cathode pads are interconnected by a metallic connections;

an anode pad extending from the front side of the photodiode array, said anode pad is positioned between a first metallic cathode pad and a second metallic cathode pad.

11. The photodiode array of claim 10 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising at least two metallic cathode pads extending from said front side of the photodiode array.

12. The photodiode of claim 10 wherein said anode pad is in physical contact with a p+ doped region.

13. The photodiode array of claim 10 wherein the layer of silicon is in the range of 80 to 200 microns thick.

14. The photodiode array of claim 10 wherein the plurality of metallic cathode pads extending from the surface of said back side of the photodiode array is in contact with a n+ doped region.

15. The photodiode array of claim 14 wherein the n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter.

16. The photodiode array of claim 10 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm.

17. The photodiode array of claim 10 wherein said photodiode array has a rise time of 40 nanoseconds or less.

18. The photodiode array of claim 10 wherein said metallic connections define a grid of at least 64 cells, each of said cells comprising a photodiode.