Three dimensional structure memory

• US 8,907,499 B2
• Filed: 01/04/2013
• Issued: 12/09/2014
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Lam, David
• Application Number:
  US13/734,874
• Publication Number:
  US 20130187290A1
• Time in Patent Office: 704 Days
• Field of Search: 257777-778, 257685-686, 365/63, 365/51, 365/230.06, 438/455, 438/977, 438/107, 438/108
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A thin and substantially flexible structure comprising:

a thin, substantially flexible monocrystalline semiconductor layer of one piece; and

a silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile.

2. The thin and substantially flexible structure of claim 1, further comprising:

a vertical interconnect conductor extending vertically through the thin semiconductor layer; and

a vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile.

3. The thin and substantially flexible structure of claim 2, wherein:

the thin semiconductor layer comprises vertical holes etched therethrough; and

the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.

4. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer is formed from a semiconductor wafer.

5. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer has a thickness of 50 microns or less.

6. The thin and substantially flexible structure of claim 4, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.

7. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer is unitary.

8. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.

9. The thin and substantially flexible structure of claim 8, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.

10. The thin and substantially flexible structure of claim 1, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.

11. The thin and substantially flexible structure of claim 2, further comprising:

a bottomside surface and a topside surface;

a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; and

an interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;

wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.

45. The thin and substantially flexible structure of claim 1, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.

49. The thin and substantially flexible structure of claim 1, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

112. The thin and substantially flexible structure of claim 1, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

122. The thin and substantially flexible structure of claim 1, wherein at least three of:

a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer;

the thin semiconductor layer is formed from a semiconductor wafer;

the thin substrate has a thickness of 50 microns;

the thin semiconductor layer is unitary;

the thin semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thin semiconductor layer;

the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

145. The thin and substantially flexible structure of claim 1, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

12. A thin and substantially flexible circuit comprising:

a thin monocrystalline semiconductor layer of one piece;

a silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile; and

circuitry supported by the thin semiconductor layer and the dielectric layer defining an integrated circuit die having an area, wherein the thin semiconductor layer extends throughout a substantial portion of the area of the integrated circuit die.

13. The thin and substantially flexible circuit of claim 12, comprising:

a vertical interconnect conductor extending vertically through the thin semiconductor layer and coupled to said circuitry; and

a vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile.

14. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer is formed from a semiconductor wafer.

15. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer has a thickness of 50 microns or less.

16. The thin and substantially flexible circuit of claim 14, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.

17. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer is unitary.

18. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.

19. The thin and substantially flexible circuit of claim 18, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.

20. The thin and substantially flexible circuit of claim 12, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.

21. The thin and substantially flexible circuit of claim 13, further comprising:

a bottomside surface and a topside surface;

a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; and

an interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;

wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.

46. The thin and substantially flexible circuit of claim 12, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.

50. The thin and substantially flexible circuit of claim 12, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

113. The thin and substantially flexible circuit of claim 12, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

123. The thin and substantially flexible circuit of claim 12, wherein at least three of:

a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer;

the thin semiconductor layer is formed from a semiconductor wafer;

the thin substrate has a thickness of 50 microns or less;

the thin semiconductor layer is unitary;

the thin semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thin semiconductor layer;

the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

146. The thin and substantially flexible circuit of claim 12, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

158. The thin and substantially flexible circuit of claim 13, wherein:

the thin semiconductor layer comprises vertical holes etched therethrough; and

the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.

22. A structure comprising:

a monocrystalline semiconductor layer of one piece; and

a silicon-based dielectric layer formed on the semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile;

wherein the semiconductor layer is capable of being thinned to obtain a thin and substantially flexible substrate.

23. The structure of claim 22, comprising:

a vertical interconnect conductor extending vertically through the thin semiconductor layer and coupled to said circuitry; and

a vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile.

25. The structure of claim 23, wherein:

the thin semiconductor layer comprises vertical holes etched therethrough; and

the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.

26. The structure of claim 23, wherein the thin semiconductor layer comprises monocystalline silicon.

27. The structure of claim 23, wherein the thin semiconductor layer is formed from a semiconductor wafer.

28. The structure of claim 23, wherein the thin semiconductor layer has a thickness of 50 microns or less.

29. The structure of claim 27, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.

30. The structure of claim 23, wherein the thin semiconductor layer is unitary.

31. The structure of claim 23, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.

32. The structure of claim 31, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.

33. The structure of claim 22, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.

34. The structure of claim 23, further comprising:

a bottomside surface and a topside surface;

a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; and

an interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;

wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.

47. The structure of claim 22, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.

51. The structure of claim 22, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

114. The structure of claim 22, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

124. The structure of claim 22, wherein at least three of:

a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer is formed from a semiconductor wafer;

the monocrystalline substrate has a thickness of 50 microns or less;

the monocrystalline semiconductor layer is unitary;

the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

147. The structure of claim 22, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

159. The structure of claim 23, further comprising:

a bottomside surface and a topside surface;

contacts formed on the bottomside surface and electrically connected to the vertical interconnect conductor; and

interconnects, contacts or circuits formed on or near the topside surface and electrically connected to the vertical interconnect conductors;

wherein the interconnects, contacts or circuits are electrically connected to the contacts on the bottomside surface via the vertical interconnects.

24. A thin and substantially flexible integrated circuit comprising:

a thin, substantially flexible monocrystalline semiconductor layer of one piece comprising integrated circuit devices; and

a silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile.

35. The thin and substantially flexible integrated circuit of claim 24, wherein:

the thin semiconductor layer comprises vertical holes etched therethrough; and

vertical interconnect conductors and vertical silicon-based dielectric insulators are formed in the vertical holes of the thin semiconductor layer.

36. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises monocystalline silicon.

37. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer is formed from a semiconductor wafer.

38. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer has a thickness of 50 microns or less.

39. The thin and substantially flexible integrated circuit of claim 37, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.

40. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer is unitary.

41. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.

42. The thin and substantially flexible integrated circuit of claim 41, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.

43. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.

44. The thin and substantially flexible integrated circuit of claim 24, further comprising:

a bottomside surface and a topside surface;

a contact formed on the bottomside surface and electrically connected to a vertical interconnect conductor; and

an interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;

wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the interconnect.

48. The thin and substantially flexible integrated circuit of claim 24, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.

52. The thin and substantially flexible integrated circuit of claim 24, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

115. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

125. The thin and substantially flexible integrated circuit of claim 24, wherein at least three of:

a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer;

the thin semiconductor layer is formed from a semiconductor wafer;

the thin substrate has a thickness of 50 microns or less;

the thin semiconductor layer is unitary;

the thin semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thin semiconductor layer;

the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

148. The thin and substantially flexible integrated circuit of claim 24, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

53. A thin and substantially flexible structure comprising:

a thinned substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer; and

a silicon-based dielectric layer formed on the thinned semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile.

54. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer has a thickness of 50 microns or less.

55. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.

56. The thin and substantially flexible structure of claim 53, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.

57. The thin and substantially flexible structure of claim 53, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprises a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

58. The thin and substantially flexible structure of claim 53, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprises a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

59. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

60. The thin and substantially flexible structure of claim 59, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

61. The thin and substantially flexible structure of claim 53, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

62. The thin and substantially flexible structure of claim 53, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

116. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

126. The thin and substantially flexible structure of claim 53, wherein at least three of:

a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer;

the thinned semiconductor layer is formed from a semiconductor wafer;

the thinned substrate has a thickness of 50 microns or less;

the thinned semiconductor layer is unitary;

the thinned semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thinned semiconductor layer;

the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

149. The thin and substantially flexible structure of claim 53, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

63. A thin and substantially flexible circuit comprising:

a thinned monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;

a silicon-based dielectric layer formed on the thinned semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile; and

circuitry supported by the thinned semiconductor layer and the dielectric layer defining an integrated circuit die having an area, wherein the thinned semiconductor layer extends throughout a substantial portion of the area of the integrated circuit die.

64. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer has a thickness of 50 microns or less.

65. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.

66. The thin and substantially flexible circuit of claim 63, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thinned semiconductor layer.

67. The thin and substantially flexible circuit of claim 63, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

68. The thin and substantially flexible circuit of claim 63, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

69. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

70. The thin and substantially flexible circuit of claim 69, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

71. The thin and substantially flexible circuit of claim 63, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

72. The thin and substantially flexible circuit of claim 63, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

117. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

127. The thin and substantially flexible circuit of claim 63, wherein at least three of:

a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer;

the thinned semiconductor layer is formed from a semiconductor wafer;

the thinned substrate has a thickness of 50 microns or less;

the thinned semiconductor layer is unitary;

the thinned semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thinned semiconductor layer;

the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

150. The thin and substantially flexible circuit of claim 63, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

73. A structure comprising:

a monocrystalline semiconductor layer of one piece formed from a semiconductor wafer; and

a silicon-based dielectric layer formed on the semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile;

wherein the monocrystalline semiconductor layer is capable of being thinned to obtain a thinned and substantially flexible substrate.

74. The structure of claim 73, wherein the monocrystalline semiconductor layer has a thickness of 50 microns or less.

75. The structure of claim 73, wherein the monocrystalline semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polished to form a polished surface.

76. The structure of claim 73, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the monocrystalline semiconductor layer.

77. The structure of claim 73, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprises a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

78. The structure of claim 73, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

79. The structure of claim 73, wherein the monocrystalline semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

80. The structure of claim 79, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

81. The structure of claim 73, comprising at least one conductive interconnection that passes vertically through the monocrystalline semiconductor layer and is insulated from the monocrystalline semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

82. The structure of claim 73, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

118. The structure of claim 73, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

128. The structure of claim 73, wherein at least three of:

a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer is formed from a semiconductor wafer;

the monocrystalline substrate has a thickness of 50 microns or less;

the monocrystalline semiconductor layer is unitary;

the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

151. The structure of claim 73, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

83. A thin and substantially flexible integrated circuit comprising:

a thinned, substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer and comprising integrated circuit devices; and

a silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile.

84. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer has a thickness of 50 microns or less.

85. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.

86. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of memory cell layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said memory cell layers in a stacked relationship to the thinned semiconductor layer.

87. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising an array of memory cells and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

88. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

89. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

90. The thin and substantially flexible integrated circuit of claim 89, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

91. The thin and substantially flexible integrated circuit of claim 83, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

92. The thin and substantially flexible integrated circuit of claim 83, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

119. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

129. The thin and substantially flexible integrated circuit of claim 83, wherein at least three of:

a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer;

the thinned semiconductor layer is formed from a semiconductor wafer;

the thinned substrate has a thickness of 50 microns or less;

the thinned semiconductor layer is unitary;

the thinned semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thinned semiconductor layer;

the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

152. The thin and substantially flexible integrated circuit of claim 83, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

93. A thin and substantially flexible structure comprising:

a thinned substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;

a plurality of deposited polysilicon layers; and

a plurality of silicon-based dielectric layers formed on the thinned semiconductor layer and polysilicon layers and having a stress of less than 5×

10⁸ dynes/cm² tensile.

94. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer has a thickness of 50 microns or less.

95. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.

96. The thin and substantially flexible structure of claim 93, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said polysilicon layers in a stacked relationship to the thinned semiconductor layer.

97. The thin and substantially flexible structure of claim 93, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

98. The thin and substantially flexible structure of claim 93, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

99. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

100. The thin and substantially flexible structure of claim 99, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

101. The thin and substantially flexible structure of claim 93, comprising at least one conductive interconnection that passes vertically through at least one of the polysilicon layers and is insulated from the at least one of the polysilicon layers by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

102. The thin and substantially flexible structure of claim 93, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

120. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

130. The thin and substantially flexible structure of claim 93, wherein at least three of:

a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer;

the thinned semiconductor layer is formed from a semiconductor wafer;

the thinned substrate has a thickness of 50 microns or less;

the thinned semiconductor layer is unitary;

the thinned semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the thinned semiconductor layer;

the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

153. The thin and substantially flexible structure of claim 93, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

103. A structure comprising:

a monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;

a plurality of memory layers; and

a plurality of silicon-based dielectric layers formed on the semiconductor layer and memory layers and having a stress of less than 5×

10⁸ dynes/cm² tensile;

wherein the monocrystalline semiconductor layer is capable of being thinned to obtain a thinned and substantially flexible substrate.

104. The structure of claim 103, wherein the monocrystalline semiconductor layer has a thickness of 50 microns or less.

105. The structure of claim 103, wherein the monocrystalline semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.

106. The structure of claim 103, further comprising at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile deposited on each of said memory layers in a stacked relationship to the monocrystalline semiconductor layer.

107. The structure of claim 103, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprising one of the memory layers and at least one low stress silicon-based dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

108. The structure of claim 103, wherein the monocrstalline semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.

109. The structure of claim 108, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

110. The structure of claim 103, comprising at least one conductive interconnection that passes vertically through at least one of the memory layers and is insulated from the at least one of the memory layers by a low stress silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

111. The structure of claim 103, comprising a logic layer for performing at least one of the following functions:

microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

121. The structure of claim 103, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

131. The structure of claim 103, wherein at least three of:

a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×

10⁸ dynes/cm² tensile;

the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer is formed from a semiconductor wafer;

the monocrystalline substrate has a thickness of 50 microns or less;

the monocrystalline semiconductor layer is unitary;

the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer;

the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer;

the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface;

the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the backside.

154. The structure of claim 103, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.

132. An integrated circuit comprising:

at least one thin, substantially flexible integrated circuit layer comprising at least a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside; and

at least one low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layer has a stress of less than 5×

10⁸ dynes/cm² tensile.

133. The integrated circuit of claim 132, further comprising a polished or smoothed backside of the thinned, substantially flexible moncrystalline semiconductor substrate, wherein the polished or smoothed backside enables the thinned, substantially flexible monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces the vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing.

134. The integrated circuit of claim 133, wherein the integrated circuit structure is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, and the at least one low stress silicon-based dielectric layer.

135. The integrated circuit of claim 133, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

136. The integrated circuit of claim 134, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

139. The integrated circuit of claim 133, further comprising a plurality of memory circuit layers in a stacked relationship with the substantially flexible integrated circuit layer and vertical interconnections interconnecting said layers, wherein a plurality of vertical interconnections pass through at least one of the plurality of memory circuit layers, wherein at least one of the plurality of memory circuit layers comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm² and an array of memory cells.

140. The integrated circuit of claim 139, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer, and low stress of the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.

141. The integrated circuit of claim 140, wherein a portion of the integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic block of the at least one thin, substantially flexible integrated circuit layer, a plurality of memory blocks one from each of the plurality of memory circuit layers and an array of vertical interconnections interconnecting the logic block and the plurality of memory blocks, wherein the array of vertical interconnections passes through at least one memory block of the plurality of memory blocks, wherein the at least one of the memory block stacks is able to perform memory operations through the array of vertical interconnections.

155. The structure of claim 133, wherein the semiconductor substrate is thinned and polished such that the semiconductor substrate is substantially flexible.

156. The integrated circuit of claim 139, wherein a process technology used to make the at least one thin, substantially flexible integrated circuit layer is different from a process technology used to make at least one of the plurality of memory circuit layers.

160. The integrated circuit of claim 133, further comprising a plurality of memory circuit layers, wherein a comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm² and an array of memory cells.

161. The integrated circuit of claim 139, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, the at least one low stress silicon-based dielectric layer, and the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.

162. The integrated circuit of claim 140, wherein a portion of the integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic portion of the at least one thin, substantially flexible integrated circuit layer, a memory portion of at least one of the plurality of memory circuit layers and vertical interconnections interconnecting the logic portion and the memory portion, wherein the at least one of the memory block stacks is able to perform memory operations.

137. A substantially flexible integrated circuit comprising:

at least one thin, substantially flexible integrated circuit layer comprising a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside, wherein the backside of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed, wherein the polished or smoothed backside enables the thinned, monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces the vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing by reducing its vulnerability to fracture as a result of flexing; and

at least one low-stress silicon-based dielectric layers formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layers have a stress of less than 5×

10⁸ dynes/cm² tensile;

wherein the substantially flexible integrated circuit is substantially flexible through combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, and the at least one low stress silicon-based dielectric layer.

138. The substantially flexible stacked integrated circuit structure of claim 137, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

142. The substantially flexible integrated circuit of claim 137, further comprising a plurality of memory circuit layers in a stacked relationship with the substantially flexible integrated circuit layer and vertical interconnections interconnecting said layers, wherein a plurality of vertical interconnections pass through at least one of the plurality of memory circuit layers, wherein at least one of the plurality of memory layers comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm² and an array of memory cells.

143. The substantially flexible integrated circuit of claim 142, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer, and low stress of the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.

144. The substantially flexible integrated circuit of claim 143, wherein a portion of the substantially flexible integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic block of the at least one thin, substantially flexible integrated circuit layer, a plurality of memory blocks one from each of the plurality of memory circuit layers and an array of vertical interconnections interconnecting the logic block and the plurality of memory blocks, wherein the array of vertical interconnections passes through at least one memory block of the plurality of memory blocks, wherein the at least one of the memory block stacks is able to perform memory operations through the array of vertical interconnections.

157. The substantially flexible integrated circuit of claim 142, wherein a process technology used to make the at least one thin, substantially flexible integrated circuit layer is different from a process technology used to make at least one of the plurality of memory circuit layers.

163. The substantially flexible integrated circuit of claim 137, further comprising a plurality of memory circuit layers, wherein a comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm² and an array of memory cells.

164. The substantially flexible integrated circuit of claim 142, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, the at least one low stress silicon-based dielectric layer, and the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.

165. The substantially flexible integrated circuit of claim 143, wherein a portion of the substantially flexible integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic portion of the at least one thin, substantially flexible integrated circuit layer, a memory portion of at least one of the plurality of memory circuit layers and vertical interconnections interconnecting the logic portion and the memory portion, wherein the at least one of the memory block stacks is able to perform memory operations.