Systems and methods for sampling in an input network of a delta-sigma modulator
First Claim
1. An input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, the input network comprising a sampling capacitor, and wherein the input network:
- during a first period of a first phase of a clock signal, drives an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of the sampling capacitor; and
during a second period of the first phase of the clock signal, samples an analog input signal onto the input plate of the sampling capacitor.
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Abstract
In accordance with systems and methods of the present disclosure, an input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, may be configured to, during a first period of a first phase of a clock signal, drive an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of a sampling capacitor integral to the input network. The input network may further be configured to, during a second period of the first phase of the clock signal, sample an analog input signal onto the input plates of the sampling capacitor.
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Citations
12 Claims
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1. An input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, the input network comprising a sampling capacitor, and wherein the input network:
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during a first period of a first phase of a clock signal, drives an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of the sampling capacitor; and during a second period of the first phase of the clock signal, samples an analog input signal onto the input plate of the sampling capacitor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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during a first period of a first phase of a clock signal, driving an analog feedback signal proportional to a digital feedback signal of a feedback digital-to-analog stage of a delta-sigma converter onto an input plate of the sampling capacitor, wherein the sampling capacitor is integral to an input sampling network for the delta-sigma converter; and during a second period of the first phase of the clock signal, sampling an analog input signal onto the input plate of the sampling capacitor. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification