Systems and methods for sampling in an input network of a delta-sigma modulator

• US 8,907,829 B1
• Filed: 05/17/2013
• Issued: 12/09/2014
• Est. Priority Date: 05/17/2013
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Naderi, Ali
• Primary Examiner(s): Lauture, Joseph
• Application Number:
  US13/896,526
• Time in Patent Office: 571 Days
• Field of Search: 341/143, 341/155, 341/156, 341/172, 341/150
• US Class Current: 341/143
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/804 with charge redistribution
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/496 Details of sampling arrangements or methods

Abstract

In accordance with systems and methods of the present disclosure, an input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, may be configured to, during a first period of a first phase of a clock signal, drive an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of a sampling capacitor integral to the input network. The input network may further be configured to, during a second period of the first phase of the clock signal, sample an analog input signal onto the input plates of the sampling capacitor.

Claims

1. An input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, the input network comprising a sampling capacitor, and wherein the input network:

during a first period of a first phase of a clock signal, drives an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of the sampling capacitor; and

during a second period of the first phase of the clock signal, samples an analog input signal onto the input plate of the sampling capacitor.

2. The input network of claim 1, wherein:

the input network further comprises a second sampling capacitor;

the analog feedback signal is an analog differential signal;

the analog input signal is an analog differential input signal;

during the first period of the first phase of a clock signal, the input network drives the analog differential feedback signal onto the input plate of the sampling capacitor and an input plate of a second sampling capacitor, such that a positive polarity of the analog differential feedback signal is driven to the sampling capacitor and a negative polarity of the analog differential feedback signal is driven to the second sampling capacitor; and

during the second period of the first phase of the clock signal, the input network samples the analog differential input signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor such that a positive polarity of the analog differential input signal is sampled on the sampling capacitor and a negative polarity of the analog differential input signal is sampled on the second sampling capacitor.

3. The input network of claim 2, wherein:

during a first period of a second phase of the clock signal, the input network drives a complement of the analog differential feedback signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor, such that the negative polarity of the analog differential feedback signal is driven to the sampling capacitor and the positive polarity of the analog differential feedback signal is driven to the second sampling capacitor; and

during a second period of the second phase of the clock signal, the input network samples a complement of the analog differential input signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor such that the negative polarity of the analog differential input signal is sampled on the sampling capacitor and the positive polarity of the analog differential input signal is sampled on the second sampling capacitor.

4. The input network of claim 1, wherein the input network further charge transfers the analog input signal from the sampling capacitor to an input of the delta-sigma modulator during a second phase of the clock signal.

5. The input network of claim 1, wherein:

the sampling capacitor is an equivalent capacitor comprising one or more physical capacitors coupled to each other at their respective output plates and configured such that during the first portion of the sampling phase of the clock signal, the input network drives a respective voltage onto an input plate of each of the one or more parallel physical capacitors such that the one or more physical capacitors are equivalent to a single capacitor being driven by the analog feedback signal during the first portion of the first phase of the clock signal.

6. The input network of claim 5, wherein each of the one or more physical capacitors are configured to be selectively coupled to either of a positive polarity of a reference voltage or a negative polarity of the reference voltage based on the digital feedback signal such that the one or more physical capacitors are equivalent to a single capacitor being driven by the analog feedback signal during the first portion of the first phase of the clock signal.

7. A method comprising:

during a first period of a first phase of a clock signal, driving an analog feedback signal proportional to a digital feedback signal of a feedback digital-to-analog stage of a delta-sigma converter onto an input plate of the sampling capacitor, wherein the sampling capacitor is integral to an input sampling network for the delta-sigma converter; and

during a second period of the first phase of the clock signal, sampling an analog input signal onto the input plate of the sampling capacitor.

8. The method of claim 7, wherein the analog feedback signal is an analog differential signal and the analog input signal is an analog differential input signal, and the method further comprises:

during the first period of the first phase of a clock signal, driving the analog differential feedback signal onto the input plate of the sampling capacitor and an input plate of a second sampling capacitor integral to the input sampling network, such that a positive polarity of the analog differential feedback signal is driven to the sampling capacitor and a negative polarity of the analog differential feedback signal is driven to the second sampling capacitor; and

during the second period of the first phase of the clock signal, sampling the analog differential input signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor such that a positive polarity of the analog differential input signal is sampled on the sampling capacitor and a negative polarity of the analog differential input signal is sampled on the second sampling capacitor.

9. The method of claim 8, further comprising:

during a first period of a second phase of the clock signal, driving a complement of the analog differential feedback signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor, such that the negative polarity of the analog differential feedback signal is driven to the sampling capacitor and the positive polarity of the analog differential feedback signal is driven to the second sampling capacitor; and

during a second period of the second phase of the clock signal, sampling a complement of the analog differential input signal onto the input plate of the sampling capacitor and the input plate of the second sampling capacitor such that the negative polarity of the analog differential input signal is sampled on the sampling capacitor and the positive polarity of the analog differential input signal is sampled on the second sampling capacitor.

10. The method of claim 7, wherein the input network further charge transfers the analog input signal from the sampling capacitor to an input of the delta-sigma modulator during a second phase of the clock signal.

11. The method of claim 7, wherein:

the sampling capacitor is an equivalent capacitor comprising one or more physical capacitors coupled to each other at their respective output plates and configured such that during the first portion of the sampling phase of the clock signal, the input network drives a respective voltage onto an input plate of each of the one or more parallel physical capacitors such that the one or more physical capacitors are equivalent to a single capacitor being driven by the analog feedback signal during the first portion of the first phase of the clock signal.

12. The method of claim 11, wherein each of the one or more physical capacitors are configured to be selectively coupled to either of a positive polarity of a reference voltage or a negative polarity of the reference voltage based on the digital feedback signal such that the one or more physical capacitors are equivalent to a single capacitor being driven by the analog feedback signal during the first portion of the first phase of the clock signal.