Semiconductor device and method of operating the same

• US 8,908,430 B2
• Filed: 07/19/2012
• Issued: 12/09/2014
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Yoo, Byoung Sung
• Primary Examiner(s): ELMS, RICHARD T
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US13/553,161
• Publication Number:
  US 20130021853A1
• Time in Patent Office: 873 Days
• Field of Search: 365/189.05, 365/189.11, 365/185.19, 365/185.25, 365/185.03, 365/185.11, 365/185.12
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

An embodiment of the present invention provides a semiconductor device, including cell string comprising a plurality of memory cells; page buffer comprising latch and switching element, wherein the switching element is coupled between the latch and the bit line which is coupled to the cell string; and a page buffer controller configured to apply a gradually rising turn-on voltage to the switching elements during a bit line setup operation of a program operation.

Claims

1. A semiconductor device, comprising:

a cell string comprising a plurality of memory cells;

a page buffer, coupled to the cell string through a bit line, comprising a latch and switching elements, wherein some of the switching elements are coupled between the latch and the bit line; and

a page buffer controller configured to selectively apply gradually rising turn-on voltages to the switching elements during a bit line setup operation of a program operation.

2. The semiconductor device of claim 1, wherein the turn-on voltages comprise staircase waveform signals.

3. The semiconductor device of claim 1, wherein the page buffer controller comprises level shifters for applying the turn-on voltages to gates of the switching elements.

4. The semiconductor device of claim 2, wherein the level shifters apply the turn-on voltages to the switching elements which are coupled between the latch and the bit line, wherein the turn-on voltages are lower than a target turn-on voltage in the beginning of the bit line setup operation of a program operation and then gradually increases up to the target turn-on voltage.

5. A method of operating a semiconductor device, comprising:

applying a program permission voltage or a program inhibition voltage to a latch of page buffer;

transferring the program permission voltage or the program inhibition voltage to the bit line by applying a gradually rising turn-on voltage to gate of a switching element coupled between the bit line and the latch; and

applying a program pass voltage to unselected word lines, and a program voltage to a selected word line to program selected memory cells.

6. The method of claim 5, wherein the turn-on voltage comprises a staircase waveform signal.

7. The method of claim 5, wherein the program permission voltage is 0 V, and the program inhibition voltage is a power source voltage.

8. The method of claim 5, wherein the turn-on voltage is lower than a target turn-on voltage in the beginning of the bit line setup operation of a program operation and then gradually increases up to the target turn-on voltage.

9. The method of claim 8, wherein the transferring of the program permission voltage or the program inhibition voltage to the bit line is performed for a specific time.

10. The method of claim 9, wherein the turn-on voltage is gradually raised at constant time intervals within the specific time.

11. A method of operating a semiconductor device, comprising:

gradually increasing electric potential at a source of a switching element, coupled between a bit line and a latch included in a page buffer coupled to cell strings through the bit line, by applying a gradually rising turn-on voltage to the switching element, before applying a program voltage to a selected word line.

12. The method of claim 11, wherein the turn-on voltage comprises a staircase waveform signal.

13. The method of claim 12, wherein the turn-on voltage is lower than a target turn-on voltage in the beginning of a bit line setup operation of a program operation and then gradually increases up to a target turn-on voltage.

14. The method of claim 11, wherein a power source voltage is applied to the latch which is coupled to a drain of the switching element in order to increase the electric potential of the source.