Non-volatile memory (NVM) with block-size-aware program/erase

• US 8,908,445 B2
• Filed: 03/15/2013
• Issued: 12/09/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: He, Chen, Wang, Yanzhuo
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/837,652
• Publication Number:
  US 20140269111A1
• Time in Patent Office: 634 Days
• Field of Search: None
• US Class Current: 365/189.011
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of the selected block; determining a set of program/erase voltages based on the array size and temperature from a temperature sensor; and programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block.

Claims

1. A method for programming/erasing a memory, the memory comprising a plurality of blocks, each block comprising a plurality of memory cells, and a set of charge pumps which apply voltages to the plurality of blocks, the method comprising:

selecting a block of the plurality of blocks;

determining an array size of the selected block, wherein the array size comprises a number of memory cells included in the selected block;

determining a set of program/erase voltages based on the array size; and

programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block.

2. The method of claim 1, wherein the set of program/erase voltages has a first set of values when the array size is a first size and a second set of values when the array size is a second size, different than the first size.

3. The method of claim 1, wherein the determining the set of program/erase voltages comprises:

determining at least one of a drain voltage, a well voltage, a gate voltage, and a source voltage to be applied by a corresponding charge pump of the set of charge pumps.

4. The method of claim 1, further comprising:

determining a temperature of the memory, wherein the determining the set of program/erase voltages is based on the array size and the temperature.

5. The method of claim 4, wherein the determining the set of program/erase voltages comprises:

accessing storage circuitry which stores sets of program/erase voltages corresponding to different array sizes at different temperatures.

6. The method of claim 4, wherein the determining the set of program/erase voltages comprises:

calculating the set of program/erase voltages using the array size and the temperature.

7. The method of claim 1, wherein the determining the set of program/erase voltages comprises:

accessing storage circuitry which stores sets of program/erase voltages corresponding to different array sizes.

8. The method of claim 1, wherein the programming/erasing the selected block comprises:

controlling the set of charge pumps to provide the set of program/erase voltages during the programming/erasing of the selected block.

9. The method of claim 1, wherein the determining the set of program/erase voltages comprises:

calculating the set of program/erase voltages using the array size.

10. The method of claim 1, wherein the programming/erasing the selected block comprises:

applying the set of program/erase voltages for a plurality of program/erase pulses.

11. The method of claim 1, wherein the determined set of program/erase voltages results in the number of program/erase pulses required to program/erase the selected block being within a predetermined range.

12. The method of claim 1, wherein the determined set of program/erase voltages results in threshold voltages of the memory cells within the selected block being within a predetermined range after the programming/erasing of the selected block.

13. A memory, comprising:

a plurality of blocks, each block comprising a plurality of memory cells;

a set of charge pumps coupled to provide program/erase voltages to the plurality of blocks; and

a memory controller, wherein the memory controller selects a block of the plurality of blocks for programming/erasing and, based on an array size of the selected block, determines a set of program/erase voltages to be provided by the set of charge pumps to the selected block during the programming/erasing of the selected block, wherein the array size comprises a number of memory cells included in the selected block.

14. The memory of claim 13, further comprising:

a temperature sensor coupled to the memory controller, wherein the memory controller determines the set of program/erase voltages based on the array size and a temperature provided by the temperature sensor.

15. The memory of claim 13, further comprising:

storage circuitry which stores sets of program/erase voltages corresponding to different array sizes, wherein the memory controller accesses the storage circuitry to determine the set of program/erase voltages.

16. The memory of claim 13, further comprising:

storage circuitry which stores sets of program/erase voltages corresponding to different array sizes at different temperatures, wherein the memory controller accesses the storage circuitry to determine the set of program/erase voltages.

17. The memory of claim 13, wherein the memory controller determines at least one of a drain voltage, a well voltage, a gate voltage, and a source voltage to be applied by a corresponding charge pump of the set of charge pumps as part of the set of program/erase voltages.

18. A method for programming/erasing a memory, the memory comprising a plurality of blocks, each block comprising a plurality of memory cells, and a set of charge pumps which apply voltages to the plurality of blocks, the method comprising:

selecting a block of the plurality of memory blocks;

determining an array size of the selected block, wherein the array size comprises a number of memory cells included in the selected block;

determining a temperature of the memory;

determining a set of program/erase voltages based on the array size and the temperature; and

programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block.

19. The method of claim 18, wherein the set of program/erase voltages has a first set of values when the array size is a first size and a second set of values when the array size is a second size, different than the first size.

20. The method of claim 18, wherein the determining the set of program/erase voltages comprises:

determining at least one of a drain voltage, a well voltage, a gate voltage, and a source voltage to be applied by a corresponding charge pump of the set of charge pumps.