Multi-column addressing mode memory system including an integrated circuit memory device

• US 8,908,466 B2
• Filed: 04/11/2013
• Issued: 12/09/2014
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Lai, Lawrence, Bellows, Chad A., Richardson, Wayne S.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/860,825
• Publication Number:
  US 20140003131A1
• Time in Patent Office: 607 Days
• Field of Search: 711/5, 711/105, 711/154, 365/189.04, 365/230.03, 365/230.06, 365/233
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Claims

1. An apparatus to interact with a memory integrated circuit characterized by a row decoder cycle time, the apparatus comprising:

a command interface to convey read commands to the memory integrated circuit; and

a data interface to receive data from the memory integrated circuit via a data interconnect responsive to the read commands;

wherein the apparatus has two operational modes, including a first operational mode in which the apparatus is to issue via the command interface a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and a second operational mode in which the apparatus is to issue via the command interface a second read command to access two columns of the open row of the memory integrated circuit within the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another.

2. The apparatus of claim 1, embodied as at least one of a memory controller or a graphics controller.

3. The apparatus of claim 2, wherein:

the command interface and data interface are embodied as a dynamic random access memory (DRAM) controller integrated circuit;

the memory integrated circuit comprises a DRAM integrated circuit; and

said apparatus further embodied as a module comprising the DRAM controller integrated circuit and the DRAM integrated circuit.

4. The apparatus of claim 1, wherein the data interface is operable to receive data from the data interconnect at a maximum data width of the data interconnect irrespective of whether the apparatus is operated in the first operational mode or the second operational mode, the maximum data width corresponding to a maximum number of bits that can be concurrently received via respective data lines of the data interconnect.

5. The apparatus of claim 4, wherein during the second operational mode, the data interface is operable to receive the data as respective columns of data corresponding to the respective column addresses in a manner where each of the respective columns of data is received at the maximum data width at respective times over the data interconnect.

6. The apparatus of claim 4, wherein, during the second operational mode, the data interface is operable to concurrently receive respective columns of data corresponding to the respective column addresses, each in a manner corresponding to a respective half of the maximum data width.

7. The apparatus of claim 1, wherein the apparatus further comprises circuitry to program a register of the memory integrated circuit to operate in a first mode, if the apparatus is to operate in the first operational mode, and a second mode, if the apparatus is to operate in the second operational mode.

8. The apparatus of claim 1, wherein the apparatus further has a third operational mode in which the apparatus is to issue via the command interface a third read command to access four columns of the open row of the memory integrated circuit within the row decoder cycle time, using four respective column addresses that can be selectively offset variable relative to one another.

9. The apparatus of claim 1, wherein the apparatus comprises circuitry to generate the second read command as a command packet having two fields adapted to each carry a different one of the respective column addresses.

10. The apparatus of claim 1, adapted for use where the memory integrated circuit comprises multiple banks, wherein the apparatus is to issue each of the read commands in a manner that contains a bank address field to select one of the multiple banks.

11. The apparatus of claim 1, wherein the respective column addresses are directed to respective halves of a page of memory.

12. An apparatus to interact with a memory integrated circuit characterized by a row decoder cycle time, the apparatus comprising:

a command interface to convey read commands to the memory integrated circuit; and

a data interface to receive data from the memory integrated circuit via a data interconnect responsive to the read commands, the data interconnect characterized by a data width corresponding to a maximum number of bits that can be concurrently received via respective data lines of the data interconnect;

wherein the apparatus has two operational modes, including

a first operational mode in which the apparatus is to issue via the command interface a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and in which the data interface is to receive read data responsive to the first read command at the data width from the data interconnect, and

a second operational mode in which the apparatus is to issue via the command interface a second read command to access two columns of the open row of the memory integrated circuit within the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another, and in which the data interface is to receive read data responsive to the second read command at the data width from the data interconnect.

13. The apparatus of claim 12, embodied as at least one of a memory controller or a graphics controller.

14. The apparatus of claim 12, wherein:

the command interface and the data interface are embodied as a dynamic random access memory (DRAM) controller integrated circuit;

the memory integrated circuit comprises a DRAM integrated circuit; and

the apparatus is further embodied as a module comprising the DRAM controller integrate circuit and the DRAM integrated circuit, wherein DRAM controller integrated circuit is operable to issue activate and precharge commands in association with each of the first read command and the second read command.

15. The apparatus of claim 12, wherein during the second operational mode, the data interface is operable to receive the data as respective columns of data corresponding to the respective column addresses in a manner where each column of data is received using the data width and where the apparatus is to receive the respective columns of data are received at different times from the data interconnect.

16. The apparatus of claim 12, wherein, during the second operational mode, the data interface is operable to concurrently receive respective columns of data corresponding to the respective column addresses, each in a manner corresponding to a respective half of the data width.

17. The apparatus of claim 12, wherein the apparatus comprises circuitry to generate the second read command as a command packet having two fields adapted to each carry a different one of the respective column addresses.

18. The apparatus of claim 12, adapted for use where the memory integrated circuit comprises multiple banks, wherein the apparatus is to issue each of the read commands in a manner that contains a bank address field to select one of the multiple banks.

19. A controller for a memory integrated circuit characterized by a row decoder cycle time, the controller comprising:

a command interface;

means for issuing read commands to the memory integrated circuit for performance during the row decoder cycle time, including a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and a second read command to access two columns of the open row of the memory integrated circuit during the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another; and

means for receiving read data from the memory integrated circuit responsive to the first read command and the second read command each at a maximum data width of a data interconnect in terms of bits that can be concurrently received via respective data lines.

20. The controller of claim 19, embodied as a dynamic random access memory (DRAM) controller, wherein the memory integrated circuit is a DRAM integrated circuit, wherein the means for issuing read commands is operable to issue activate and precharge commands in association with each of the first read command and the second read command, and wherein the respective column addresses are directed to respective halves of a page of memory.