Methods and apparatus for signaling on a differential link

• US 8,908,807 B2
• Filed: 01/14/2009
• Issued: 12/09/2014
• Est. Priority Date: 03/14/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenborn, Zale T.
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): VARNDELL, ROSS E
• Application Number:
  US12/353,527
• Publication Number:
  US 20090122905A1
• Time in Patent Office: 2,155 Days
• Field of Search: 375/244, 375/257, 375/317, 375/318, 340/10.33, 257/532, 327/108, 327/333, 327/20, 327/18, 327/1, 327/65
• US Class Current: 375/317
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Claims

1. A receiver for use with a differential serial data link including at least two lines, the receiver comprising:

a difference detector to develop an output signal representative of a voltage difference between the at least two lines of the differential serial data link;

an integrator to integrate the output signal to develop an integrated signal;

a first signaling circuit connected to an output of the integrator to signal a first component of the receiver when the integrated signal from the output of the integrator exceeds a first threshold to cause the first component of the receiver to transition from a first state to a second state;

a second signaling circuit to signal a second component of the receiver when the integrated signal exceeds a second threshold which is higher than the first threshold; and

an AC coupling circuit associated with the differential serial data link and including at least two AC coupling capacitors and at least two shunt impedances, wherein the AC coupling capacitors, the shunt impedances, and a RC circuit of the integrator are dimensioned such that the AC coupling circuit passes a signal sufficient to develop the integrated signal exceeding the first threshold in response to a first DC difference signal of a first predetermined duration and a first predetermined magnitude being received via the differential serial data link at the AC coupling circuit;

wherein the first state is a first reduced power state and the second state is a second reduced power state wherein the receiver relays an in-band signal to a second receiver via a second differential serial data link;

wherein the integrated signal exceeds the second threshold when the first difference signal and a second difference signal are received in succession via the differential serial data link associated with the first and second signaling circuits.

2. A receiver as defined in claim 1 wherein the integrated signal exceeds the second threshold when the first difference signal and a second difference signal are received in succession by the AC coupling circuit.

3. A receiver as defined in claim 1 wherein the first state is a reduced power state and the second state is a normal power state.

4. A receiver as defined in claim 1 wherein the first state is a reduced power state and the second state is a reset state.

5. A receiver as defined in claim 1 wherein the first or second difference signal is due to a DC common mode shift.

6. A receiver as defined in claim 1 wherein the difference detector comprises an operational amplifier.

7. A receiver as defined in claim 6 wherein the operational amplifier has low gain.

8. A receiver as defined in claim 6 further comprising a rectifier to rectify an output signal of the operational amplifier prior to integration.