Method for managing and controlling the low power modes for an integrated circuit device

• US 8,909,956 B2
• Filed: 06/10/2010
• Issued: 12/09/2014
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhuang, Zhiqing, Fadavi-Ardekani, Jalil, Bhasin, Vinay Kumar, Madar, Lawrence John III, Zhang, Chenmin, Rakshani, Vafa James
• Primary Examiner(s): Yanchus, III, Paul
• Assistant Examiner(s): KINSEY, BRANDON MICHAEL
• Application Number:
  US12/813,265
• Publication Number:
  US 20100257393A1
• Time in Patent Office: 1,643 Days
• Field of Search: 713/300, 713/320, 710/260
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention'"'"'s state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Claims

1. A power management unit configured to manage power modes of an electronic integrated circuit (IC) device having a processor, the power management unit comprising:

a wake up event detection logic circuit configured to;

trigger a transition between multiple power modes including a first RUN mode and a second RUN mode, wherein the processor is configured to execute code during the first RUN mode and the second RUN mode, and

ignore an external event during the transition from the first RUN mode to the second RUN mode.

2. The power management unit of claim 1, further comprising:

an inter-integrated circuit (I2C) bus driver coupled to the wake up event detection logic circuit, wherein the I2C bus driver is configured to drive an external power management unit via an I2C bus; and

a data transfer circuit coupled to the wake up event detection logic circuit, wherein the data transfer circuit is configured to write data to the external power management unit using the I2C bus.

3. The power management unit of claim 1, further comprising:

a sequencer state machine configured to store voltage levels for the multiple power modes, wherein the multiple power modes include the first RUN mode, the second RUN mode, a HIBERNATE mode, and a POWERDOWN mode;

a timer configured to control wait times during which a second external event triggers a second transition between the multiple power modes;

a control register circuit configured to store information about operating parameters of the power management unit; and

a register file circuit configured to store settings for the first RUN mode, the HIBERNATE mode and the POWERDOWN mode.

4. The power management unit of claim 3, wherein the sequencer state machine is configured to provide zero voltage to the electronic IC device when a state of the sequencer state machine corresponds to the POWERDOWN mode.

5. The power management unit of claim 3, wherein the control register circuit comprises:

a programmable register controlled by a high speed clock configured to be gated off after the programmable register has been programmed.

6. The power management unit of claim 5, further comprising:

an external clock manager configured to start and stop the high speed clock.

7. The power management unit of claim 5, wherein the control register circuit is run by the high speed clock.

8. The power management unit of claim 3, wherein the register file circuit is configured to store operating voltage settings for transitions between the first RUN mode, the POWERDOWN mode and the HIBERNATE mode.

9. The power management unit of claim 3, wherein the power management unit is driven by a low frequency clock.

10. The power management unit of claim 9, further comprising:

an external clock manager configured to start and stop the low frequency clock.

11. The power management unit of claim 3, wherein the control register circuit is configured to receive commands from the processor.

12. The power management unit of claim 3, wherein the sequencer state machine is configured to store commands written by an external host.

13. The power management unit of claim 3, wherein the control register circuit is configured to require an input of a security access code to access the control register set.

14. A method for controlling power modes of an integrated circuit (IC) having a processor, the method comprising:

transitioning from a first power mode of a plurality of power modes to a second power mode of the plurality of power modes, wherein the plurality of power modes include a first RUN mode and a second RUN mode, and where the processor is configured to execute code during the first RUN mode and the second RUN mode; and

ignoring an external event when transitioning from the first RUN mode to the second RUN mode until the transitioning is complete.

15. The method of claim 14, wherein the plurality of power modes includes a POWERDOWN mode, and wherein the transitioning from the first RUN mode to the POWERDOWN mode includes the steps of:

stopping a clock and a power supply;

counting down to zero from a pre-programmed value;

stopping counting before zero is reached if a second external event is detected;

sending a request to a clock manager if zero is reached;

waiting for an acknowledgement from the clock manager;

switching to a voltage level corresponding to the POWERDOWN mode if zero is reached; and

monitoring for a third external event after switching a voltage applied to the IC to the voltage level.

16. The method of claim 14, wherein the plurality of power modes includes a POWERDOWN mode, and wherein transitioning from the POWERDOWN mode to the first RUN mode includes the steps of:

detecting a wake up event; and

switching a voltage applied to the IC to a voltage level corresponding to the first RUN mode.

17. The method of claim 14, wherein the plurality of power modes includes a HIBERNATE mode, and wherein transitioning from the first RUN mode to the HIBERNATE mode includes the steps of:

stopping a clock;

counting down to zero from a pre-programmed value;

stopping counting before zero is reached if a second external event is detected;

sending a request to a clock manager if zero is reached;

waiting for an acknowledgement from the clock manager;

switching to a voltage level corresponding to the HIBERNATE mode if zero is reached; and

monitoring for a third external event after switching to the voltage level.

18. The method of claim 14, wherein the plurality of power modes includes a HIBERNATE mode, and wherein transitioning from the HIBERNATE mode to the first RUN mode includes the steps of:

detecting a wake up event; and

switching a voltage applied to the IC to a voltage level corresponding to the first RUN mode.

19. The method of claim 14, wherein the plurality of power modes includes a HIBERNATE mode and a POWERDOWN mode, and wherein transitioning from the HIBERNATE mode to the POWERDOWN mode includes the steps of:

counting down to zero from a pre-programmed value;

switching a voltage applied to the IC to a voltage level corresponding to the POWERDOWN mode;

ignoring any external event until the switching is complete; and

monitoring for any external event after switching to the voltage level.

20. The method of claim 14, wherein the transitioning from the first RUN mode to the second RUN mode includes:

switching a voltage applied to the IC to a voltage level corresponding to the second RUN mode.

21. The method of claim 14, further comprising:

assigning a respective IC voltage level range to the multiple power modes including;

the first RUN mode,

a HIBERNATE mode,

a POWERDOWN mode, and

the second RUN mode operating at a second voltage range different from a first voltage of the first RUN mode;

controlling wait times during which the external event triggers a transition between the first RUN mode, the HIBERNATE mode and the POWERDOWN mode; and

controlling transitions between the multiple power modes by changing a voltage applied to the IC between respective ranges of voltage levels.

22. A system, comprising:

a processor configured to execute code during a first low power mode and a second low power mode;

a sequencer configured to manage a transition between a plurality of power modes including the first low power mode, the second low power mode, and a third low power mode; and

a wake up event detection logic circuit configured to;

trigger a first transition between the first low power mode and the second low power mode,

ignore a first external event when the sequencer is managing the first transition,

trigger a second transition between the first low power mode and the third low power mode, and

stop the second transition if a second external event is detected during the second transition.

23. The system of claim 22, wherein the first low power mode is a first RUN mode, and wherein the second low power mode is a second RUN mode.

24. The system of claim 22, wherein the sequencer is configured to manage the first transition independently from the processor.

25. The system of claim 23, wherein the third low power mode is a HIBERNATE mode or a POWERDOWN mode, wherein the processor is configured to not execute code during the HIBERNATE mode, and wherein the processor is configured to not execute code during the POWERDOWN mode.

26. The system of claim 23, wherein the third low power mode is a HIBERNATE mode, wherein the plurality of power modes further includes a POWERDOWN mode, and wherein the wake up event detection logic circuit is further configured to stop a third transition between the MBERNATE mode and the POWERDOWN mode if a third external event is detected during the third transition.