System and method for detecting copyback programming problems

• US 8,909,982 B2
• Filed: 10/31/2011
• Issued: 12/09/2014
• Est. Priority Date: 06/19/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Weston-Lewis, Graeme Moffat, Prins, Douglas Alan, Olbrich, Aaron Keith
• Primary Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US13/285,892
• Publication Number:
  US 20120324277A1
• Time in Patent Office: 1,135 Days
• Field of Search: 711/103
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Claims

1. A method of detecting errors in a copyback operation in a flash memory device, the method comprising:

in the flash memory device with a controller, prior to a copyback operation, programming a page of data such that a subset of the page of data includes a predetermined sequence of bits;

performing the copyback operation by;

internally copying the page of data from a first non-volatile portion in a flash memory chip of the flash memory device to a volatile portion of the flash memory device;

copying the subset of the page of data from the volatile portion of the flash memory device to memory associated with the controller;

detecting the presence of one or more errors by analyzing the data subset copied to the memory associated with the controller, wherein analyzing the data subset includes determining whether the data subset includes the predetermined sequence of bits; and

in accordance with detecting the presence of the one or more errors in the data subset;

verifying all of the data copied to the volatile portion, the verifying including correcting detected errors; and

storing the verified data to a second non-volatile portion of the flash memory chip.

2. The method of claim 1, wherein the first non-volatile portion, the second non-volatile portion and the volatile portion of the flash memory device are included in the flash memory chip of the flash memory device, and the controller and the memory associated with the controller are included in a system controller chip that is separate from the flash memory chip in the flash memory device.

3. The method of claim 1, wherein the detecting includes detecting a quantity of errors, the method further comprising in accordance with a determination that the quantity of errors exceeds a predetermined threshold, preventing copyback operations, subsequent to the copyback operation, for the first non-volatile portion of the flash memory chip.

4. The method of claim 1, wherein verifying all of the data copied to the volatile portion further comprises correcting the one or more errors detected.

5. The method of claim 1, wherein the detecting includes detecting a quantity of errors, the method further comprising, in accordance with a determination that the quantity of errors exceeds a predetermined threshold, determining whether to reclaim the first non-volatile portion of the flash memory chip.

6. The method of claim 1, wherein the first non-volatile portion of the flash memory chip comprises a block of the flash memory chip, and the data copied from the first non-volatile portion in the flash memory chip of the flash memory device is copied from the block of the flash memory chip and comprises a page of data.

7. A flash memory device configured to detect errors in a copyback operation, the flash memory device comprising:

a flash memory chip comprising a first non-volatile portion, a second non-volatile portion, and a volatile portion; and

a controller in communication with the flash memory chip, the controller configured to;

program a page of data such that a subset of the page of data includes a predetermined sequence of bits;

command the flash memory chip to internally copy the page of data from the first non-volatile portion to the volatile portion of the flash memory device;

copy the subset of the page of data from the volatile portion of the flash memory device to memory associated with the controller;

detect the presence of one or more errors by analyzing the data subset copied to the memory associated with the controller, wherein analyzing the data subset includes determining whether the data subset includes the predetermined sequence of bits; and

command the flash memory chip to in accordance with detecting the presence of the one or more errors in the data subset;

verify all of the data copied to the volatile portion, the verifying including correcting detected errors; and

storing the verified data to a second non-volatile portion of the flash memory chip.

8. The flash memory device of claim 7, wherein the first non-volatile portion, the second non-volatile portion and the volatile portion of the flash memory device are included in the flash memory chip of the flash memory device, and the controller and the memory associated with the controller are included in a system controller chip that is separate from the flash memory chip in the flash memory device.

9. The flash memory device of claim 7, wherein the controller is configured to detect a quantity of errors in the subset of the data, and the controller is further configured to in accordance with a determination that the quantity of errors exceeds a predetermined threshold, prevent copyback operations, subsequent to the copyback operation, for the first non-volatile portion of the flash memory chip.

10. The flash memory device of claim 7, wherein the controller is configured to verify all of the data copied to the volatile portion by at least correcting the one or more errors detected.

11. The flash memory device of claim 7, wherein the controller is configured to detect a quantity of errors, and the controller is further configured to in accordance with a determination that the quantity of errors exceeds a predetermined threshold, determine whether to reclaim the first non-volatile portion of the flash memory chip.

12. The flash memory device of claim 7, wherein the first non-volatile portion of the flash memory chip comprises a block of the flash memory chip, and the data copied from the first non-volatile portion in the flash memory chip of the flash memory device is copied from the block of the flash memory chip and comprises a page of data.