Semiconductor device that detects abnormalities of watchdog timer circuits

• US 8,909,997 B2
• Filed: 07/12/2011
• Issued: 12/09/2014
• Est. Priority Date: 07/12/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Fuchigami, Takashi
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US13/181,193
• Publication Number:
  US 20120011407A1
• Time in Patent Office: 1,246 Days
• Field of Search: None
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36

Abstract

A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.

Claims

1. A semiconductor device comprising:

an arithmetic and logic unit;

a first watchdog timer used for runaway monitoring of the arithmetic and logic unit;

a second watchdog timer used for runaway monitoring of the arithmetic and logic unit;

first to third clock sources, and

first to third diagnosis circuits, wherein

the first diagnosis circuit monitors the second watchdog timer and generates a first diagnosis result signal indicating whether a monitoring result is abnormal or not,

the third diagnosis circuit monitors the first watchdog timer and generates a second diagnosis result signal indicating whether a monitoring result is abnormal or not,

the second diagnosis circuit determines whether the first diagnosis circuit is abnormal or not based on the first diagnosis result signal, and determines whether the third diagnosis circuit is abnormal or not based on the second diagnosis result signal,

the first clock source supplies a clock to the first watchdog timer and the second diagnosis circuit,

the second clock source supplies a clock to the first diagnosis circuit and the arithmetic and logic unit, and

the third clock source supplies a clock to the second watchdog timer and the third diagnosis circuit.

2. The semiconductor device according to claim 1, wherein

the second diagnosis circuit determines whether the second watchdog timer is abnormal or not based on the first diagnosis result signal, and determines whether the first watchdog timer is abnormal or not based on the second diagnosis result signal.

3. The semiconductor device according to claim 1, wherein

the second diagnosis circuit generates a first operation notification signal indicating whether the second diagnosis circuit is operating normally or not, and

at least one of the first diagnosis circuit and the third diagnosis circuit determines whether the second diagnosis circuit is abnormal or not based on the first operation notification signal.

4. The semiconductor device according to claim 3, wherein

each of the first to third diagnosis circuits includes an abnormal part identifying circuit,

the second diagnosis circuit monitors the first diagnosis circuit and generates a third diagnosis result signal indicating whether a monitoring result is abnormal or not,

the first diagnosis circuit generates a second operation notification signal indicating whether the first diagnosis circuit is operating normally or not,

the third diagnosis circuit generates a third operation notification signal indicating whether the third diagnosis circuit is operating normally or not, and

the abnormal part identifying circuit included in each of the first to third diagnosis circuits identifies an abnormal part based on the first to third diagnosis result signals and the first to third operation notification signals.

5. The semiconductor device according to claim 4, wherein the abnormal part identifying circuit included in each of the first to third diagnosis circuits

determines that the second watchdog timer is abnormal when the first diagnosis result signal is not supplied, the second operation notification signal is normally supplied, and a monitoring result by the second or third diagnosis circuit is normal,

determines that the first diagnosis circuit is abnormal when the first diagnosis result signal is not supplied, the second operation notification signal is not supplied, and a monitoring result by the second or third diagnosis circuit is normal,

determines that the first diagnosis circuit is abnormal when the first diagnosis result signal is not supplied, the second operation notification signal is not supplied, and a monitoring result by the second diagnosis circuit is abnormal,

determines that the first diagnosis circuit is abnormal when the third diagnosis result signal is not supplied, the first operation notification signal is normally supplied, and a monitoring result by the first or third diagnosis circuit is normal,

determines that the second diagnosis circuit is abnormal when the third diagnosis result signal is not supplied, the first operation notification signal is not supplied, and a monitoring result by the first or third diagnosis circuit is normal,

determines that the first watchdog timer is abnormal when the second diagnosis result signal is not supplied, the third operation notification signal is normally supplied, and a monitoring result by the first or second diagnosis circuit is normal, and

determines that the third diagnosis circuit is abnormal when the second diagnosis result signal is not supplied, the third operation notification signal is not supplied, and a monitoring result by the first or second diagnosis circuit is normal.

6. The semiconductor device according to claim 4, further comprising:

first to third clock sources, wherein

the first clock source supplies a clock to the first watchdog timer and the second diagnosis circuit,

the second clock source supplies a clock to the first diagnosis circuit and the arithmetic and logic unit, and

the third clock source supplies a clock to the second watchdog timer and the third diagnosis circuit.

7. The semiconductor device according to claim 6, wherein

the first diagnosis circuit determines a monitoring result of the second watchdog timer based on whether there is a count notified from the second watchdog timer while the clock from the second clock source is notified a specified number of times,

the second diagnosis circuit determines a monitoring result of the first diagnosis circuit based on whether there is a count notified from the first diagnosis circuit while the clock from the first clock source is notified a specified number of times, and

the third diagnosis circuit determines a monitoring result of the first watchdog timer based on whether there is a count notified from the first watchdog timer while the clock from the third clock source is notified a specified number of times.

8. The semiconductor device according to claim 6, wherein

the first diagnosis circuit determines that a frequency anomaly is occurring in the third clock source when the count notified from the second watchdog timer while the clock from the second clock source is notified a specified number of times exceeds a specified threshold value,

the second diagnosis circuit determines that a frequency anomaly is occurring in the second clock source when the count notified from the first diagnosis circuit while the clock from the first clock source is notified a specified number of times exceeds a specified threshold value, and

the third diagnosis circuit determines that a frequency anomaly is occurring in the first clock source when the count notified from the first watchdog timer while the clock from the third clock source is notified a specified number of times exceeds a specified threshold value.

9. The semiconductor device according to claim 8, wherein

the arithmetic and logic unit turns off a clock source where a frequency anomaly is occurring.

10. The semiconductor device according to claim 1, wherein

the first diagnosis circuit determines that a frequency anomaly is occurring in the third clock source when the count notified from the second watchdog timer while the clock from the second clock source is notified a specified number of times exceeds a specified threshold value.

11. The semiconductor device according to claim 1, wherein

the second diagnosis circuit determines that a frequency anomaly is occurring in the second clock source when the count notified from the first diagnosis circuit while the clock from the first clock source is notified a specified number of times exceeds a specified threshold value.

12. The semiconductor device according to claim 1, wherein

the third diagnosis circuit determines that a frequency anomaly is occurring in the first clock source when the count notified from the first watchdog timer while the clock from the third clock source is notified a specified number of times exceeds a specified threshold value.

13. A calculator comprising the semiconductor device according to claim 1.

14. A semiconductor device, comprising:

an arithmetic and logic unit;

a first watchdog timer used for runaway monitoring of the arithmetic and logic unit;

a second watchdog timer used for runaway monitoring of the arithmetic and logic unit; and

first to third diagnosis circuits, wherein

the first diagnosis circuit monitors the second watchdog timer and generates a first diagnosis result signal indicating whether a monitoring result is abnormal or not,

the third diagnosis circuit monitors the first watchdog timer and generates a second diagnosis result signal indicating whether a monitoring result is abnormal or not,

the second diagnosis circuit determines whether the first diagnosis circuit is abnormal or not based on the first diagnosis result signal, and determines whether the third diagnosis circuit is abnormal or not based on the second diagnosis result signal,

the second diagnosis circuit generates a first operation notification signal indicating whether the second diagnosis circuit is operating normally or not, and

the second diagnosis circuit monitors the first diagnosis circuit and generates a third diagnosis result signal indicating whether a monitoring result is abnormal or not.

15. A semiconductor device comprising:

an arithmetic and logic unit;

a first watchdog timer configured to receive a first signal from the arithmetic and logic unit;

a second watchdog timer configured to receive a second signal from the arithmetic and logic unit; and

a plurality of diagnosis circuits including;

a first diagnosis circuit;

a second diagnosis circuit; and

a third diagnosis circuit,

the first diagnosis circuit being configured to receive a third signal from the second watchdog timer, and to output a fourth signal to the arithmetic and logic unit based on the third signal,

the third diagnosis circuit being configured to receive a fifth signal from the first watch dog timer, and to output a sixth signal to the arithmetic and logic unit based on the fifth signal, and

the second diagnosis circuit being configured to receive a seventh signal from the first diagnosis circuit and an eighth signal from the third diagnosis circuit, and to output a ninth signal to the arithmetic and logic unit based on the seventh signal and the eighth signal.