Intelligent bit recovery for flash memory

• US 8,910,020 B2
• Filed: 10/31/2011
• Issued: 12/09/2014
• Est. Priority Date: 06/19/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Frayer, Jack Edward, Olbrich, Aaron Keith, Stonelake, Paul Roger, Kulkarni, Anand Krishnamurthi, Ma, Yale Yueh
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US13/285,873
• Publication Number:
  US 20120324276A1
• Time in Patent Office: 1,135 Days
• Field of Search: 714/718, 714/42, 714/6.11, 714/746, 714/764, 714/799, 714/E11.023, 714/E11.029, 714/2, 714/37, 714/54, 714/758, 365/185.33, 711/E12.008, 711/E12.103
• US Class Current: 714/764
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method and system for intelligent bit recovery identifies toggling bits, which change in value from one read to the next, and examines a subset of potential bit patterns. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify a problem, or plurality of problems, that is potentially causing the toggling bits, and to select the subset of potential bit patterns as potential solutions. The subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

Claims

1. A method of recovery of bits in a flash memory device, the method performed by a controller of the flash memory device, the method comprising:

at the controller of the flash memory device;

determining N bits of data for recovery, wherein the N bits of data comprise a subset of bits of data read in a read operation and N is an integer greater than 1;

selecting, based at least in part on one or more aspects of the flash memory device, a plurality of potential bit patterns of the N bits, wherein a count of plurality of potential bit patterns is less than 2^N; and

after selecting the plurality of potential bit patterns, iteratively determining whether a potential bit pattern of the plurality of potential bit patterns enables recovery of at least one or more of the N bits.

2. The method of claim 1, wherein the N bits of data for recovery are determined by reading multiple times a set of bits that include the N bits of data to identify the N bits of data as bits of data having inconsistent value across the multiple readings.

3. The method of claim 1, further comprising, identifying one or more potential problems with the flash memory device;

and

wherein the plurality of potential bit patterns are selected based in part on the one or more identified potential problems.

4. The method of claim 3, wherein identifying the one or more potential problems includes analyzing test bits to identify one of over-programming or loss retention.

5. The method of claim 1, wherein the plurality potential bit patterns are selected based at least in part on a type of at least a portion of the flash memory device.

6. The method of claim 1, wherein the plurality potential bit patterns are selected based at least in part on whether the N bits of data for recovery are in single level cells or multilevel cells.

7. The method of claim 1, wherein the plurality of potential bit patterns are selected based at least in part on values of the N bits of data for recovery.

8. The method of claim 1, wherein the plurality of potential bit patterns are selected independent of values of the N bits of data for recovery.

9. The method of claim 1, wherein the flash memory device includes multilevel cells;

and

wherein the N bits for recovery are in a page under recovery; and

wherein the plurality of potential bit patterns are selected based at least in part on which bit in the multi-level cell is subject to recovery.

10. The method of claim 9, wherein the multi-level cells comprise 2-bit multilevel cells with an upper page and a lower page;

wherein the page under recovery is the upper page;

wherein a paired page corresponding to the page under recovery is the lower page; and

wherein the plurality of potential bit patterns are selected based at least in part on values of bits in the lower page.

11. The method of claim 1, wherein iteratively determining whether the plurality of potential bit patterns enable recovery of at least one or more of the N bits comprises analyzing the plurality of potential bit patterns with error correction coding.

12. A method of recovering bits in a flash memory device, the method performed by a controller of the flash memory device, the method comprising:

at the controller of the flash memory device;

determining N bits of data for recovery wherein the N bits of data comprise a subset of bits of data read in a read operation and N is an integer greater than 1;

selecting a plurality of potential bit patterns for correction of one or more potential flash memory problems with the N bits, wherein a count of the plurality of potential bit patterns is less than 2^N;

after selecting the plurality of potential bit patterns, iteratively determining whether a potential bit pattern of the plurality of potential bit patterns enables recovery of at least one or more of the N bits and recovering a subset of the N bits using a selected bit pattern of the plurality of potential bit patterns; and

after recovering the subset of the N bits, recovering remaining bits of the N bits using ECC correction.

13. The method of claim 12, wherein the plurality of potential bit patterns are selected for correction of one or both of over-programming and retention loss.

14. The method of claim 12, wherein determining N bits of data for recovery by reading multiple times a set of bits that include the N bits of data to identify the N bits of data as bits of data having inconsistent value across the multiple reading times.

15. The method of claim 14, further comprising determining M bits of data that are further in error;

and

wherein iteratively determining whether the potential bit patterns enable recovery of at least one or more of the N bits comprises determining whether one of the plurality of potential bit patterns recovers a predetermined number of bits to correct for N+M error bits.

16. A flash memory device comprising:

a memory; and

a controller in communication with the memory, the controller configured to;

determine N bits of data in the memory for recovery, wherein the N bits of data comprise a subset of bits of data read in a read operation and N is an integer greater than 1;

select, based at least in part on one or more aspects of the flash memory device, a plurality of potential bit patterns of the N bits, wherein a count of the plurality of potential bit patterns is less than 2^N; and

after selecting the plurality of potential bit patterns, iteratively determine whether a potential bit pattern of the plurality of potential bit patterns enables recovery of at least one or more of the N bits.

17. The flash memory device of claim 16, wherein the controller is configured to determine the N bits of data for recovery by reading multiple times a set of bits that include the N bits of data to identify the N bits of data as bits of data having inconsistent value across the multiple reading times.

18. The flash memory device of claim 16, further comprising, identifying one or more potential problems with the flash memory device;

and

wherein the plurality of potential bit patterns are selected based at least in part on the one or more identified potential problems.

19. The flash memory device of claim 18, wherein the controller is configured to identify the one or more potential problems by analyzing test bits to identify one of over-programming or loss retention.

20. The flash memory device of claim 16, wherein the controller is configured to select the plurality of potential bit patterns based at least in part on a type of at least a portion of the flash memory device.

21. The flash memory device of claim 16, wherein the controller is configured to select the plurality of potential bit patterns based at least in part on whether the N bits of data for recovery are in a single level cells or multi-level cells.

22. The flash memory device of claim 16, wherein the controller is configured to select the plurality of potential bit patterns based at least in part on values of the N bits of data for recovery.

23. The flash memory device of claim 16, wherein the controller is configured to select the plurality of potential bit patterns independent of values of the N bits of data for recovery.

24. The flash memory device of claim 16, wherein the memory includes multilevel cells;

wherein the N bits for recovery are in a page under recovery; and

wherein the controller is configured to select the plurality of potential bit patterns based at least in part on which bit in the multi-level cell is subject to recovery.

25. The flash memory device of claim 24, wherein the multi-level cells comprise 2-bit multi-level cells with an upper page and a lower page;

wherein the page under recovery is the upper page;

wherein a paired page corresponding to the page under recovery is the lower page; and

wherein the controller is configured to select the plurality of potential bit patterns based at least in part of values of one or more bits in the lower page.

26. The flash memory device of claim 16, wherein the controller is configured to iteratively determine whether the plurality of potential bit patterns enable recovery of at least one or more of the N bits by analyzing the plurality of potential bit patterns with error correction coding.

27. A flash memory device comprising

a memory;

and

a controller in communication with the memory, the controller configured to;

determine N bits of data for recovery, wherein the N bits of data comprise a subset of bits of data read in a read operation and N is an integer greater than 1;

select a plurality of potential bit patterns for correction of the one or more potential flash memory problems with the N bits, wherein a count of the plurality of potential bit patterns is less than 2^N;

after selecting the plurality of potential bit patterns, iteratively determine whether a potential bit pattern of the plurality of potential bit patterns enables recovery of at least one or more of the N bits and recovering a subset of the N bits using a selected bit pattern of the plurality of potential bit patterns; and

after recovering the subset of the N bits, recovering remaining bits of the N bits using ECC correction.

28. The flash memory device of claim 27, wherein the controller is configured to select the plurality of potential bit patterns for correction of one or both of over-programming and retention loss.

29. The flash memory device of claim 27, wherein the controller is configured to determine N bits of data for recovery by reading multiple times a set of bits that include the N bits of data to identify the N bits of data having inconsistent value across the multiple reading times.

30. The flash memory device of claim 29, wherein the controller is further configured to determine M bits of data are further in error;

and

wherein the controller is configured to iteratively determine whether the plurality of potential bit patterns enable recovery of at least one or more of the N bits by determining whether one of the potential bit patterns recovers a predetermined number of bits to correct for N+M error bits.