Model based simulation method with fast bias contour for lithography process check

• US 8,910,092 B1
• Filed: 11/13/2013
• Issued: 12/09/2014
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Ying-Chou, Liu, Ru-Gun, Shih, I-Chang, Chiu, Feng-Yuan, Chen, Chiu Hsiu
• Primary Examiner(s): Lin, Sun
• Application Number:
  US14/078,729
• Time in Patent Office: 391 Days
• Field of Search: 716/50, 716/51, 716/53, 716/54
• US Class Current: 716/53
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.

Claims

1. A method, comprising:

receiving a target layout design having a geometric pattern thereon;

using a computing unit to apply a set of fast-bias contour (FBC) rules to the target layout design to provide an electronic photomask having FBC-edits that differentiate the electronic photomask from the target layout design, wherein the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design; and

performing a lithography process check on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design;

wherein the lithography process check includes a Monte-Carlo process where a plurality of device parameters are randomly varied for a plurality of simulations to characterize how semiconductor devices are expected to be manufactured based on the electronic photomask, which includes the FBC-edits.

2. The method of claim 1, wherein the FBC rules alter patterns for individual layers of the target layout design by using a math function or table-lookup to approximate OPC without actually performing OPC.

3. The method of claim 2, wherein the FBC rules alter patterns for individual layers of the target layout design by using one of the following math functions:

a Hermite polynomial, a Bezier curve, a Lagrange polynomial, a Gaussian function, a divergence function, or a Bessel function.

4. The method of claim 2, wherein applying the FBC rules comprises:

identifying instances of a first geometric shape in the target layout design;

performing a table-look-up of a first FBC-modified geometric shape, which is based on the first geometric shape, from a plurality of predetermined FBC-modified geometric shapes; and

generating the electronic photomask by replacing the instances of the first geometric shape in the target layout design with corresponding instances of the first FBC-modified geometric shape.

5. The method of claim 4, wherein applying the FBC rules further comprises:

identifying instances of a second geometric shape in the target layout design;

performing a table-look-up of a second FBC-modified geometric shape, which is based on the second geometric shape, from the plurality of predetermined FBC-modified geometric shapes; and

generating the electronic photomask by replacing the instances of the second geometric shape in the target layout design with corresponding instances of the second FBC-modified geometric shape.

6. A method, comprising:

receiving a target layout design having a geometric pattern thereon;

using a computing unit to apply a set of fast-bias contour (FBC) rules to the target layout design to provide an electronic photomask having FBC-edits that differentiate the electronic photomask from the target layout design, wherein the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design;

performing a lithography process check on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design;

setting a manufacturing yield criteria;

determining whether a plurality of simulation results for the plurality of simulations, respectively, meet performance metrics specified for the target layout design; and

providing a simulated yield result which specifies how many of the simulation results meet the performance metrics specified for the target layout design.

7. The method of claim 6, further comprising:

selectively providing an error message based on whether the simulated yield result is less than the manufacturing yield criteria.

8. A method, comprising:

receiving a target layout design having multiple layers with multiple geometric patterns thereon;

using a computing unit to identify instances of a first geometric shape on a first layer of the target layout design;

using a computing unit to apply a set of fast-bias contour (FBC) rules to the identified instances of the first geometric shape to generate an electronic photomask having FBC-edits that differentiate the electronic photomask from the target layout design;

performing a lithography process check on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design;

wherein the FBC rules alter patterns for individual layers of the target layout design by using one of the following math functions;

a Hermite polynomial, a Bezier curve, a Lagrange polynomial, a Gaussian function, a divergence function, or a Bessel function.

9. The method of claim 8, wherein the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design.

10. The method of claim 8, wherein the FBC-rules alter patterns for individual layers of the target layout design by using a math function or table-lookup to approximate OPC without actually performing OPC.

11. The method of claim 8, wherein applying the FBC rules comprises:

identifying instances of a first geometric shape in the target layout design;

performing a table-look-up of a first FBC-modified geometric shape, which is based on the first geometric shape, from a plurality of predetermined FBC-modified geometric shapes; and

generating the electronic photomask by replacing the instances of the first geometric shape in the target layout design with corresponding instances of the first FBC-modified geometric shape.

12. The method of claim 8, further comprising:

setting a manufacturing yield criteria;

determining whether a plurality of simulation results for the plurality of simulations, respectively, meet performance metrics specified for the target layout design; and

providing a simulated yield result which specifies how many of the simulation results meet the performance metrics specified for the target layout design.

13. The method of claim 12, further comprising:

flagging an error if the simulated yield result does not meet the performance metrics to trigger revision of the target layout design.

14. The method of claim 12, further comprising:

if the simulated yield result meets the performance metrics, then performing optical proximity correction to further verify the target layout design.

15. A circuit simulation tool, comprising:

a computing unit operably coupled to a memory unit via one or more busses;

wherein the memory unit is configured to store digitized data representing a target layout design, computer executable lithography process check (LPC) instructions, computer executable fast-bias contour (FBC) instructions, and optical proximity correction (OPC) instructions;

wherein the computing unit is configured to apply the FBC instructions on the target layout design to generate a photomask with FBC edits, and then apply the LPC instructions to determine whether a sufficient percentage of devices manufactured using the photomask are expected to operate at minimum performance metrics.

16. The circuit simulation tool of claim 15, wherein the computing unit is configured to flag an error and not apply the OPC instructions to the target layout design in cases when the photomask with FBC edits fails LPC testing.

17. The circuit simulation tool of claim 15, wherein the LPC instructions carry out a Monte Carlo simulation using the photomask.

18. The circuit simulation tool of claim 17, wherein if the photomask with FBC edits passes LPC testing, then the OPC instructions are applied to the target layout design to generate an OPC-edited layout design, which may include additional polygons and lines/edges that are moved relative to the target layout design.