Systems and methods for determining effective capacitance to facilitate a timing analysis

• US 8,910,101 B1
• Filed: 10/11/2013
• Issued: 12/09/2014
• Est. Priority Date: 10/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chao-Yang, Yeh, Cheng-Hung, Huang, Chi-Ting
• Primary Examiner(s): Garbowski, Leigh
• Application Number:
  US14/051,522
• Time in Patent Office: 424 Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector

Abstract

A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Claims

1. A method for timing analysis using a processor, comprising:

generating a model that is representative of a coupling between at least two through substrate vias (“

TSVs”

);

determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determining an effective capacitance value corresponding to each respective impedance value;

populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and

conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network.

2. The method of claim 1, wherein determining an impedance profile between the at least two TSVs comprises determining an impedance profile between the at least two TSVs as a function of different spacing values.

3. The method of claim 2, wherein determining an effective capacitance value comprises determining an effective capacitance value at each of the different spacing values.

4. The method of claim 1, wherein conducting an RC extraction comprises conducting an RC extraction of the design layout based on capacitance values that are approximately half of each of the effective capacitance values to generate the RC network.

5. The method of claim 4, wherein the model has each of the at least two TSVs coupled to ground by a respective capacitor having the capacitance values that are approximately half of each of the effective capacitance values.

6. The method of claim 5, wherein the model excludes a coupling noise between the at least two TSVs.

7. The method of claim 6, further comprising performing a full chip static timing analysis using the RC network.

8. The method of claim 1, wherein the effective capacitance values vary based on frequency and based on locations of TSVs within an IC.

9. The method of claim 1, wherein conducting an RC extraction comprises conducting an RC extraction of the design layout using respectively different effective capacitance values for TSVs assigned to different signal groups.

10. The method of claim 1, the RC extraction uses respectively different effective capacitance values for TSVs located in different regions of an IC having respectively different TSV densities.

11. A system comprising:

a non-transient machine readable storage medium storing a model that is representative of a coupling between at least two through substrate vias (“

TSVs”

) generated by an electronic design automation (“

EDA”

) tool; and

an RC tool and a static timing analysis (“

STA”

) tool within the EDA tool such that the EDA tool is configured to;

determine an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determine an effective capacitance value corresponding to each respective impedance value;

conduct an RC extraction of a design layout of a TSV circuit based on respective effective capacitance values to generate an RC network, where the effective capacitance values vary based on frequency and based on locations of TSVs within an IC; and

use the RC network for a timing analysis.

12. The system of claim 11, wherein the EDA tool is configured to determine the effective capacitance value at each of the different frequency values and different spacing values.

13. The system of claim 11, wherein the EDA tool is configured to determine the impedance profile between the at least two TSVs as a function of different spacing values.

14. The system of claim 13, wherein the EDA tool is configured to determine the effective capacitance value at each of the different spacing values.

15. The system of claim 11, wherein the EDA tool is configured to conduct the RC extraction of the design layout using predefined capacitance values that are approximately half of each of the effective capacitance values.

16. The system of claim 11, wherein the EDA tool is configured to conduct the RC extraction of the design layout using respectively different effective capacitance values for TSVs located in different regions of an IC.

17. At least one non-transitory computer-readable storage medium having computer-executable instructions embodied thereon, wherein, when executed by at least one processor, the computer-executable instructions cause the at least one processor to:

provide a model that is representative of a coupling between at least two through substrate vias (“

TSVs”

);

determine an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determine an effective capacitance value corresponding to each respective impedance value;

store at least one table with respective impedance values and respective effective capacitance values for each respective frequency value, the stored impedance values and effective capacitance values accessible by the at least one processor; and

conduct an RC extraction of a design layout of a TSV circuit based on the effective capacitance values in the table to generate an RC network.

18. The at least one non-transitory computer-readable storage medium of claim 17, wherein the computer-executable instructions cause the at least one processor to determine the impedance profile between the at least two TSVs as a function of different frequency values and different spacing values.

19. The at least one non-transitory computer-readable storage medium of claim 18, wherein the computer-executable instructions cause the at least one processor to determine the effective capacitance value at each of the different frequency values and different spacing values.

20. The at least one non-transitory computer-readable storage medium of claim 17, wherein the computer-executable instructions further cause the at least one processor to use the RC network for a timing analysis.