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Systems and methods for determining effective capacitance to facilitate a timing analysis

  • US 8,910,101 B1
  • Filed: 10/11/2013
  • Issued: 12/09/2014
  • Est. Priority Date: 10/11/2013
  • Status: Active Grant
First Claim
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1. A method for timing analysis using a processor, comprising:

  • generating a model that is representative of a coupling between at least two through substrate vias (“

    TSVs”

    );

    determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

    determining an effective capacitance value corresponding to each respective impedance value;

    populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and

    conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network.

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