Systems and methods for determining effective capacitance to facilitate a timing analysis
First Claim
1. A method for timing analysis using a processor, comprising:
- generating a model that is representative of a coupling between at least two through substrate vias (“
TSVs”
);
determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;
determining an effective capacitance value corresponding to each respective impedance value;
populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and
conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network.
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Abstract
A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.
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Citations
20 Claims
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1. A method for timing analysis using a processor, comprising:
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generating a model that is representative of a coupling between at least two through substrate vias (“
TSVs”
);determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determining an effective capacitance value corresponding to each respective impedance value; populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system comprising:
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a non-transient machine readable storage medium storing a model that is representative of a coupling between at least two through substrate vias (“
TSVs”
) generated by an electronic design automation (“
EDA”
) tool; andan RC tool and a static timing analysis (“
STA”
) tool within the EDA tool such that the EDA tool is configured to;determine an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determine an effective capacitance value corresponding to each respective impedance value; conduct an RC extraction of a design layout of a TSV circuit based on respective effective capacitance values to generate an RC network, where the effective capacitance values vary based on frequency and based on locations of TSVs within an IC; and use the RC network for a timing analysis. - View Dependent Claims (12, 13, 14, 15, 16)
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17. At least one non-transitory computer-readable storage medium having computer-executable instructions embodied thereon, wherein, when executed by at least one processor, the computer-executable instructions cause the at least one processor to:
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provide a model that is representative of a coupling between at least two through substrate vias (“
TSVs”
);determine an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determine an effective capacitance value corresponding to each respective impedance value; store at least one table with respective impedance values and respective effective capacitance values for each respective frequency value, the stored impedance values and effective capacitance values accessible by the at least one processor; and conduct an RC extraction of a design layout of a TSV circuit based on the effective capacitance values in the table to generate an RC network. - View Dependent Claims (18, 19, 20)
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Specification