Method of designing a high performance application specific integrated circuit accelerator
First Claim
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1. A method of making a digital signal processing (DSP) accelerator comprising:
- operating an electronic design automation (EDA) tool to define a software programmable fully pre-laid out macro by laying out a control logic with a fixed topology to obtain a fully pre-laid out control logic;
operating the EDA tool to define a hardware programmable partially pre-laid out macro by customizing a configurable layout area and mapping a computational logic based on computation kernels for use by an application to obtain a partially pre-laid out computational logic; and
operating the EDA tool to perform a final customizing step by defining fixed area and fixed connections of the partially pre-laid out computational logic to the fully pre-laid out control logic.
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Abstract
A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
26 Citations
23 Claims
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1. A method of making a digital signal processing (DSP) accelerator comprising:
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operating an electronic design automation (EDA) tool to define a software programmable fully pre-laid out macro by laying out a control logic with a fixed topology to obtain a fully pre-laid out control logic; operating the EDA tool to define a hardware programmable partially pre-laid out macro by customizing a configurable layout area and mapping a computational logic based on computation kernels for use by an application to obtain a partially pre-laid out computational logic; and operating the EDA tool to perform a final customizing step by defining fixed area and fixed connections of the partially pre-laid out computational logic to the fully pre-laid out control logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of making a digital signal processing (DSP) accelerator comprising:
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operating an electronic design automation (EDA) tool to define a software programmable fully pre-laid out macro by laying out a control logic with a fixed topology to obtain a fully pre laid-out control logic by laying out synchronization, control, and data routing logic with a fixed topology; operating the EDA tool to define a hardware programmable partially pre-laid out macro by customizing a configurable layout area and mapping a computational logic based on computation kernels for use by an application to obtain a partially pre-laid out computational logic; operating the EDA tool to perform a final customizing step by defining fixed area and fixed connections of the partially pre-laid out computational logic to the fully pre-laid out control logic; and verifying and characterizing design behavior and timing of the fully pre-laid out control logic. - View Dependent Claims (13, 14)
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15. A digital signal processing (DSP) accelerator comprising:
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a software programmable fully pre-laid out control logic; a hardware programmable partially pre-laid out computational logic based on computation kernels for use by an application; and fixed area and fixed connections coupling the partially pre-laid out computational logic to the fully pre-laid out control logic. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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Specification