Virtualizing interrupt priority and delivery

• US 8,910,158 B2
• Filed: 12/14/2011
• Issued: 12/09/2014
• Est. Priority Date: 12/14/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Neiger, Gilbert, Sankaran, Rajesh M., Gerzon, Gideon, Uhlig, Richard A., Ghetie, Sergiu D., Neve de Mevergnies, Michael, Karrar, Adil
• Primary Examiner(s): An, Meng
• Assistant Examiner(s): Lee, James J
• Application Number:
  US13/325,714
• Publication Number:
  US 20130159579A1
• Time in Patent Office: 1,091 Days
• US Class Current: 718/1
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2213/0058 Bus-related hardware virtualisation
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/45541 Bare-metal, i.e. hypervisor runs directly on hardware
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

Claims

1. A processor for virtualizing interrupt prioritization and delivery comprising:

an instruction hardware to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events;

an execution hardware to execute the first instruction, the execution of the first instruction to include determining a first virtual processor-priority value by computing the maximum of a highest priority virtual interrupt in-service field of a virtual machine control structure and a virtual task-priority register value, and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller;

the execution hardware to determine;

in non-root mode, whether a virtual interrupt is to be delivered by comparing a highest priority virtual interrupt-requested field of the virtual machine control structure and the first processor-priority value, and to deliver the virtual interrupt in response to determining that the highest priority virtual interrupt-requested field is greater than the first virtual processor-priority value, or to hold the virtual interrupt pending in response to determining that the highest priority virtual interrupt-requested field is not greater than the first virtual processor-priority value; and

in non-root mode, whether the virtual interrupt is to be delivered at a boundary between a second instruction and a third instruction by determining whether delivery of virtual interrupts is masked at the boundary, and to deliver the virtual interrupt in response to determining that delivery of virtual interrupts is unmasked, or to execute the third instruction in non-root mode in response to determining that delivery of virtual interrupts is masked.

2. The processor of claim 1, wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to write a task-priority value to a task-priority register by computing the maximum of the task-priority value and a highest priority virtual interrupt in-service field of a virtual machine control structure to determine a second virtual processor-priority value.

3. The processor of claim 2, wherein the execution hardware is also to determine whether the virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the second virtual processor-priority value.

4. The processor of claim 1, wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to send a self-interprocessor interrupt by computing the maximum of a self-interprocessor interrupt vector and a highest priority virtual interrupt-requested field of a virtual machine control structure to determine a new highest priority virtual interrupt-requested value.

5. The processor of claim 4, wherein the execution hardware is also to determine whether the virtual interrupt is to be recognized by comparing the new highest priority virtual interrupt-requested value and the first virtual processor-priority value.

6. The processor of claim 1, wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to write to an end-of-interrupt register by clearing a bit in a virtual copy of an in-service register, the bit corresponding to a highest priority virtual interrupt in-service field in a virtual machine structure.

7. A method for virtualizing interrupt prioritization and delivery comprising:

receiving, by a processor, a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events;

executing, by the processor, the first instruction, where execution includes determining a first virtual processor-priority value by computing the maximum of a highest priority virtual interrupt in-service field of a virtual machine control structure and a virtual task-priority register value, and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller;

determining, in non-root mode, whether a virtual interrupt is to be delivered by comparing a highest priority virtual interrupt-requested field of the virtual machine control structure and the first virtual processor priority value, and to deliver the virtual interrupt in response to determining that the highest priority virtual interrupt-requested field is greater than the first virtual processor-priority value, or to hold the virtual interrupt pending in response to determining that the highest priority virtual interrupt-requested field is not greater that the first virtual processor-priority;

determining, in non-root mode, whether delivery of virtual interrupts is masked at a boundary between a second instruction to be executed and a third instruction; and

delivering the virtual interrupt in response to determining that delivery of virtual interrupts is unmasked or executing the third instruction in non-root mode in response to determining that delivery of virtual interrupts is masked.

8. The method of claim 7, further comprising responding, within the non-root mode, to an attempt by the guest software to write a task priority value to a task-priority register by computing the maximum of the task-priority value and a highest priority virtual interrupt in-service field of a virtual machine control structure to determine a second virtual processor-priority value.

9. The method of claim 8, further comprising determining whether the virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the second virtual processor-priority value.

10. The method of claim 7, further comprising responding, within the non-root mode, to an attempt by the guest software to send a self-interprocessor interrupt by computing the maximum of a self-interprocessor interrupt vector and a highest priority virtual interrupt-requested field of a virtual machine control structure to determine a new highest priority virtual interrupt-requested value.

11. The method of claim 10, further comprising determining whether the virtual interrupt is to be recognized by comparing the new highest priority virtual interrupt-requested value and the first virtual processor-priority value.

12. The method of claim 7, further comprising responding, within a non-root mode, to an attempt by the guest software to write to an end-of-interrupt register by clearing a bit in a virtual copy of an in-service register, the bit corresponding to a highest priority virtual interrupt in-service field in a virtual machine structure.

13. A system for virtualizing interrupt prioritization and delivery comprising:

a memory; and

a processor including

an instruction hardware to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events;

an execution hardware to execute the first instruction, the execution of the first instruction to include determining a virtual processor-priority value by computing the maximum of a highest priority virtual interrupt in-service field of a virtual machine control structure in the memory and a virtual task-priority register value, and storing the first virtual processor-priority value in the memory in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller;

the execution hardware to determine;

in non-root mode, whether a virtual interrupt is to be delivered by comparing a highest priority virtual interrupt-requested field of the virtual machine control structure and the first processor-priority value, and to deliver the virtual interrupt in response to determining that the highest priority virtual interrupt-requested field is greater than the first virtual processor-priority value, or to hold the virtual interrupt pending in response to determining that the highest priority virtual interrupt-requested field is not greater than the first virtual processor-priority value; and

in non-root mode, whether the virtual interrupt is to be delivered at a boundary between a second instruction and a third instruction by determining whether delivery of virtual interrupts is masked at the boundary, and to deliver the virtual interrupt in response to determining that delivery of virtual interrupts is unmasked, or to execute the third instruction in non-root mode in response to determining that delivery of virtual interrupts is masked.