Methods for making light emitting diodes and optical elements

• US 8,912,022 B2
• Filed: 12/27/2012
• Issued: 12/16/2014
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Hon Hai Precision Industry Co., Ltd., Tsinghua University
• Original Assignee: Hon Hai Precision Industry Co., Ltd., Tsinghua University
• Inventors: Jin, Yuan-Hao, Li, Qun-Qing, Fan, Shou-Shan
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Peterson, Erik T
• Application Number:
  US13/728,076
• Publication Number:
  US 20130260493A1
• Time in Patent Office: 719 Days
• Field of Search: 438/22, 438/27, 438/29, 438/32, 438/710
• US Class Current: 438/29
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/58 Optical field-shaping elements

Abstract

A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A first electrode and a second electrode are formed to electrically connect with the first semiconductor layer and the second semiconductor pre-layer respectively. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures are formed on the second semiconductor pre-layer and the patterned mask layer is removed. A method for making an optical element is also provided.

Claims

1. A method for making a light emitting diode, comprising steps of:

providing a substrate having a first surface;

forming a first semiconductor layer, an active layer, and a second semiconductor pre-layer on the first surface;

electrically connecting a first electrode with the first semiconductor layer and a second electrode with the second semiconductor pre-layer; and

applying a patterned mask layer on a second semiconductor pre-layer surface away from the active layer, wherein the patterned mask layer comprises a plurality of linear walls aligned side by side, and a groove is defined between each adjacent linear walls to form an exposed portion of the second semiconductor pre-layer; and

etching the exposed portion of the second semiconductor pre-layer surface and removing the patterned mask layer to form a plurality of three-dimensional structures, wherein during the step of etching the exposed portion of the second semiconductor pre-layer surface, the patterned mask layer remains;

the plurality of three-dimensional structures are linear protruding structures, and a cross-section of each linear protruding structure is an arc, the step of etching the exposed portion of the second semiconductor pre-layer surface is carried out in a microwave plasma system capable of producing a reactive atmosphere, the reactive atmosphere comprises chlorine gas and argon gas, a chlorine input flow rate is lower than an argon input flow rate, and the chlorine input flow rate is in a range from about 4 standard-state cubic centimeters per minute to about 20 standard-state cubic centimeters per minute, and the argon input flow rate is in a range from about 10 standard-state cubic centimeters per minute to about 60 standard-state cubic centimeters per minute.

2. The method of claim 1, wherein the plurality of linear walls are uniformly distributed in the patterned mask layer to form an array.

3. The method of claim 2, wherein the plurality of linear walls in the array are equidistantly arranged, concentric circularly arranged, or concentric rectangle arranged.

4. The method of claim 1, wherein the plurality of linear walls are arranged along a straight line, a curvy line, or a polygonal line.

5. The method of claim 1, wherein a width of the plurality of linear walls ranges from about 200 nm to about 1000 nm, and a distance between each adjacent linear walls ranges from about 10 nm to about 1000 nm.

6. The method of claim 1, wherein the step of applying the patterned mask layer on the second semiconductor pre-layer surface comprises the sub-steps of:

applying a mask layer on the second semiconductor pre-layer surface by spin coating, slit coating, slit and spin coating, or dry film lamination; and

forming a plurality of grooves in the mask layer to expose the portion of the second semiconductor pre-layer surface by electron beam lithography method, photolithography method, or nanoimprint lithography method, thus forming the patterned mask layer.

7. The method of claim 1, wherein the step of forming the first semiconductor layer comprises the sub-steps of:

applying a first semiconductor pre-layer on the first surface of the substrate;

forming a plurality of second three-dimensional structures on a first semiconductor pre-layer surface of the first semiconductor pre-layer away from the substrate.

8. The method of claim 7, wherein the active layer is grown via a horizontal epitaxial growth method.

9. A method for making a light emitting diode, comprising steps of:

providing a substrate having a first surface;

forming a first semiconductor layer, an active layer and a second semiconductor pre-layer on the first surface of the substrate, wherein the step of forming the first semiconductor layer comprises the sub-steps of;

applying a first semiconductor pre-layer on the first surface of the substrate; and

forming a plurality of second three-dimensional structures on a first semiconductor pre-layer surface of the first semiconductor pre-layer away from the substrate;

electrically contacting a first electrode with the first semiconductor layer;

electrically contacting a second electrode with the second semiconductor pre-layer; and

applying a patterned mask layer on a second semiconductor pre-layer surface away from the active layer, wherein the patterned mask layer comprises a plurality of linear walls aligned side by side, and a groove is defined between each adjacent linear walls to form an exposed portion of the second semiconductor pre-layer surface; and

etching the exposed portion of the second semiconductor pre-layer surface along a first direction and a second direction to form a plurality of three-dimensional structures and removing the patterned mask layer by dissolving the patterned mask layer in a stripping agent, wherein during the step of etching the exposed portion of the second semiconductor pre-layer surface, the patterned mask layer remains;

the first direction is perpendicular to the second semiconductor pre-layer surface, and the second direction is paralleled to the second semiconductor pre-layer surface.

10. The method of claim 9, wherein a width of the groove ranges from about 100 nm to about 200 nm;

and a distance between each adjacent grooves ranges from about 300 nm to about 400 nm.

11. The method of claim 9, wherein the exposed portion of the second semiconductor pre-layer surface is etched by a reactive atmosphere comprising chlorine gas and argon gas, and a chlorine input flow rate is lower than an argon input flow rate.