Method of fabricating and correcting nanoimprint lithography templates

• US 8,912,103 B2
• Filed: 11/20/2012
• Issued: 12/16/2014
• Est. Priority Date: 04/05/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Heo, Jin-Seok, Yeo, Jeong-Ho
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/681,468
• Publication Number:
  US 20130267095A1
• Time in Patent Office: 756 Days
• Field of Search: 257/E21.317, 257/E21.487
• US Class Current: 438/795
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10T 29/49 Method of mechanical manufacture

Abstract

A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.

Claims

1. A method of fabricating a nanoimprint lithography template, comprising:

fabricating a first nanoimprint lithography template having a plurality of chip areas;

forming a plurality of pattern areas corresponding to the plurality of chip areas on a semiconductor wafer using the first nanoimprint lithography template;

determining a deviation of a layout of the pattern areas from a desired layout of the pattern area; and

fabricating a second nanoimprint lithography template that corrects the deviation, wherein fabricating the second nanoimprint lithography template that corrects the deviation comprises;

installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage, and a template stage;

mounting a template substrate on the template stage; and

exposing regions on the template substrate with light emitted by the light source in a scanning process performed by the scanning lithography equipment, characterized in that at least one part of the scanning lithography equipment is inclined such that a line passing through a center of light exposing each of the regions, respectively, in a first direction in which the light propagates towards the template substrate is incident on the exposure region at an oblique angle.

2. The method of claim 1, wherein the scanning process includes passing the light through an elongated slit interposed between the reticle and the template substrate with respect to an optical axis of the equipment extending in said direction in which the light propagates towards the template substrate.

3. The method of claim 2, wherein the scanning process includes moving the reticle stage and the template stage in a second direction perpendicular to the first direction in which the slit is elongated.

4. The method of claim 3, wherein the scanning process is characterized in that the reticle stage is inclined relative to the template substrate.

5. The method of claim 3, wherein the scanning process includes moving the template stage to be inclined.

6. The method of claim 1, wherein the scanning process comprises tilting the reticle stage.

7. The method of claim 1, wherein the scanning process comprises raising or lowering a part of the reticle stage to tilt the reticle.

8. The method of claim 1, wherein the scanning process comprising tilting the template stage.

9. The method of claim 1, wherein the second nanoimprint lithography template has a second plurality of chip areas each including a plurality of the exposure regions, and all of the second plurality of chip areas are exposed during said scanning process.

10. The method of claim 1, wherein a size of the second nanoimprint lithography template is at least as great as that of the semiconductor wafer, and the chip areas occupy an area as great as that of areas of the semiconductor wafer to be patterned.

11. The method of claim 1, wherein forming the plurality of pattern areas on the semiconductor wafer includes:

forming a target layer and a polymer layer on the semiconductor wafer;

imprinting a pattern of the chip areas of the first nanoimprint lithography template all at once in the polymer layer, and forming a polymer pattern corresponding to the plurality of chip areas;

patterning the target layer using the polymer pattern as an etch mask; and

removing the polymer pattern.

12. The method of claim 1, wherein determining the deviation comprises measuring a bias of the pattern areas.

13. The method of claim 12, wherein fabricating the second nanoimprint lithography template that corrects the deviation includes calculating the oblique angle based on said deviation.

14. The method of claim 1, wherein fabricating the second nanoimprint lithography template that corrects the deviation includes calculating the oblique angle based on said deviation.

15. The method of claim 1, wherein fabricating the first nanoimprint lithography template having a plurality of chip areas comprises scanning regions of a substrate corresponding to the chip areas, respectively, sequentially each by a single independent scanning process.