Structure and method for MOSFETS with high-K and metal gate structure

• US 8,912,610 B2
• Filed: 04/03/2012
• Issued: 12/16/2014
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Sun, Yun-Ju, Chang, Shih-Hsun, Chen, Chia-Jen, Yamamoto, Tomonari, Kuo, Chih-Wei, Ting, Kuo-Chiang, Lin, Jr Jung, Sun, Meng-Yi
• Primary Examiner(s): Lee, Jae
• Assistant Examiner(s): Mirsalahuddin, Junaiden
• Application Number:
  US13/438,451
• Publication Number:
  US 20130119487A1
• Time in Patent Office: 987 Days
• Field of Search: 257151-153, 257/249, 257314-320, 257/331, 257/366, 257/387, 257/412, 257E29125-E29131, 257E29134-E29138, 257E2914-E29161, 257/E29.275, 257/E29.319, 257E21176-E21186, 257/E21.374, 257/E21.458, 257E21621-E21624, 257E21635-E21638, 257/E21.634, 257/E21.407, 257/E27.064, 257/E21.639, 257/E21.66, 257/E21.689, 257/E27.081, 257/E27.088, 257/E21.648, 257/E27.089, 257/E29.255, 257/E21.409, 257/E29.253, 257/192, 257/288, 257/296, 257/E21.158, 257/E21.19, 257/E21.199, 257/E21.205, 257/E21.312, 257/E21.429, 257/E21, 257/E21.444, 257/E21.453, 257/E21.507, 257/E21.64, 257/E29.157, 257/194, 257/195, 257/200, 257/295, 257/305, 257/321, 257/500, 257/E21.047, 257/E21.2, 257/E21.206, 257/E21.218, 257/E21.335, 257/E21.41, 257/E21.435, 257/E21.439, 257/E21.44, 257/E21.443, 257/E21.454, 257/E21.576, 257/E21.619, 257/E21.626, 257/E23.132, 257/E29.004, 257/E29.021, 257/E29.04, 257/E29.041, 257/E29.05, 257/E29.089, 257/E29, 438/157, 438/176, 438/195, 438/267, 438/283, 438585-596
• US Class Current: 257/407
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate; and

a gate stack disposed on the semiconductor substrate, wherein the gate stack includes;

a high k dielectric material layer,

a capping layer disposed on the high k dielectric material layer, and

a metal layer disposed on the capping layer, wherein a top surface of the metal layer includes a first width dimension, and wherein an opposing bottom surface of the metal layer includes a second width dimension less than the first width dimension,

wherein the capping layer and the high k dielectric material layer have a footing structure, wherein the capping layer of the footing structure includes a third width dimension greater than the second width dimension, and wherein the high k dielectric material layer of the footing structure includes a fourth width dimension greater than the third width dimension.

2. The semiconductor structure of claim 1, wherein the footing structure has a horizontal dimension ranging between about 0.5 nm and about 2.5 nm along a gate length direction of the gate stack.

3. The semiconductor structure of claim 1, wherein the metal layer includes:

a work function metal film disposed on the capping layer; and

another metal film on the work function metal film.

4. The semiconductor structure of claim 1, wherein the capping layer includes titanium nitride.

5. The semiconductor structure of claim 1, further comprising an interfacial layer disposed between the semiconductor substrate and the high k dielectric material layer.

6. The semiconductor structure of claim 1, wherein the metal layer includes a reentrant sidewall profile.

7. The semiconductor structure of claim 6, wherein the sidewall of the metal layer has an angle to a top surface of the semiconductor substrate, and the angle ranges between about 85 degrees and about 90 degrees.

8. A semiconductor structure, comprising:

a semiconductor substrate; and

a gate stack disposed on the semiconductor substrate, wherein the gate stack includes;

a gate dielectric layer including a high k dielectric material layer, wherein a top surface of the gate dielectric layer includes a first width dimension,

a capping layer disposed on the high k dielectric material layer, wherein a top surface of the capping layer includes a second width dimension less than the first width dimension,

a metal layer disposed on the capping layer, wherein the metal layer has a reentrant sidewall profile, and wherein a bottom surface of the metal layer includes a third width dimension less than the second width dimension,

an interfacial layer interposed between the gate dielectric layer and the semiconductor substrate, and

gate spacers formed on sidewalls of the metal layer and on the top surface of the capping layer and on the top surface of the gate dielectric layer without being formed on a top surface of the interfacial layer.

9. The semiconductor structure of claim 8, wherein:

the semiconductor substrate has a top surface wherein the gate stack is disposed on; and

the metal layer has a sidewall tilted to the top surface of the semiconductor substrate with an angle being less than about 90 degrees.

10. The semiconductor structure of claim 9, wherein the angle is greater than about 85 degrees.

11. The semiconductor structure of claim 8, wherein the gate dielectric layer and the capping layer includes a footing feature.

12. The semiconductor structure of claim 11, wherein the footing feature has a dimension along a gate length direction, wherein the dimension ranges between about 0.5 nm and about 2.5 nm.

13. The semiconductor structure of claim 8, wherein

the capping layer includes titanium nitride.

14. The semiconductor structure of claim 8, wherein the metal layer includes:

a work function metal film disposed on the capping layer; and

another metal film disposed on the work function metal film.

15. A semiconductor device comprising:

a semiconductor substrate;

a gate dielectric layer disposed on the semiconductor substrate, wherein a top surface of the gate dielectric layer includes a first dimension,

a capping layer disposed on the gate dielectric layer, wherein a top surface of the capping layer includes a second dimension less than the first dimension, and

a gate metal layer disposed on the capping layer, wherein a bottom surface of the gate metal layer includes a third dimension less than the second dimension, and wherein a top surface of the gate metal layer includes a fourth dimension greater than the third dimension;

an interfacial layer interposed between the gate dielectric layer and the semiconductor substrate; and

gate spacers formed on sidewalls of the gate metal layer and on the top surface of the capping layer and on the top surface of the gate dielectric layer without being formed on a top surface of the interfacial layer.

16. The semiconductor device of claim 15, wherein the gate metal layer includes a work function metal film disposed on the capping layer and another metal film disposed on the work function metal film,

wherein the work function metal film is in physical contact with the top surface of the capping layer and the gate spacers.