Wafer-level package and method of manufacturing the same

• US 8,912,662 B2
• Filed: 01/30/2013
• Issued: 12/16/2014
• Est. Priority Date: 05/31/2012
• Status: Active Grant

• Current Assignee: STS Semiconductor & Tele Communications Company Limited
• Original Assignee: STS Semiconductor & Tele Communications Company Limited
• Inventors: Chun, Jung Hwan
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US13/753,862
• Publication Number:
  US 20130320518A1
• Time in Patent Office: 685 Days
• Field of Search: 257/723, 257/724, 257/778, 257/787, 257/777, 257/686
• US Class Current: 257/777
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

Claims

1. A wafer-level package comprising:

a first semiconductor chip on an upper side of which an active surface facing downward is disposed;

a redistribution formed on the active surface of the first semiconductor chip;

a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique;

a copper (Cu) post and a first solder ball sequentially disposed on the redistribution;

a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip; and

a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

2. The package of claim 1, wherein the copper post and the first solder ball are formed apart from the second semiconductor chip.

3. The package of claim 1, wherein the second semiconductor chip has a smaller width than the first semiconductor chip.

4. The package of claim 1, further comprising a first heat sink disposed on a top surface of the first semiconductor chip.

5. The package of claim 1, further comprising a second heat sink disposed on a bottom surface of the second semiconductor chip.

6. The package of claim 1, wherein the redistribution is electrically connected to a pad of the first semiconductor chip.

7. The package of claim 1, wherein the bottom surface of the first solder ball is at the same level as the inactive surface of the second semiconductor chip.