Compliant printed circuit wafer probe diagnostic tool

• US 8,912,812 B2
• Filed: 05/27/2010
• Issued: 12/16/2014
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): DICKINSON, DUSTIN R
• Application Number:
  US13/318,038
• Publication Number:
  US 20120062270A1
• Time in Patent Office: 1,664 Days
• Field of Search: 32475601-75607, 32476301-76302, 32476201-76209, 32475403-7542
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.

Claims

1. A diagnostic tool for testing a wafer-level integrated circuit (IC) device coupled to testing electronics, the diagnostic tool comprising:

a first diagnostic tool adapted to be located at a first interface between a wafer probe and the wafer-level IC device, the first diagnostic tool comprising;

a first compliant printed circuit comprising a flexible polymeric sheet with a plurality of contact pads contacting distal ends of probe members in the wafer probe at a first interface and raised probe members located on the compliant printed circuit in an array contacting a plurality of contact pads on the wafer-level IC device at the first interface;

a plurality of conductive traces printed on the first compliant printed circuit and electrically coupling to the plurality of contact pads; and

a plurality of electrical devices printed on the first compliant printed circuit at a position external to the first interface, the electrical devices coupled to the conductive traces and configured to provide one or more of continuity testing at the first interface or functionality testing of the wafer-level IC device.

2. The diagnostic tool of claim 1, wherein the conductive traces comprise substantially rectangular cross-sectional shapes.

3. The diagnostic tool of claim 1, wherein a conductive material, a non-conductive material, and a semi-conductive material are printed on a single layer of the compliant printed circuit.

4. The diagnostic tool of claim 1, further comprising raised probe members printed on the compliant printed circuit in an array configured to electrically couple with the plurality of contact pads on the wafer-level IC device.

5. The diagnostic tool of claim 1, wherein the electrical devices comprise at least one of a capacitor, a resistor, a filter, a signal or power altering and enhancing device, a capacitive coupling feature, a memory device, an embedded integrated circuit, and a RF antennae.

6. The diagnostic tool of claim 1, wherein the first compliant printed circuit comprises one or more printed layers comprising one or more of a dielectric layer, a ground plane, or a power plane.

7. The diagnostic tool of claim 1, further comprising a second diagnostic tool coupled to an IC testing device and including a plurality of contact pads configured to form an electrical interconnect with proximal ends of the probe members in the wafer probe at a second interface.

8. The diagnostic tool of claim 7, wherein the IC testing device is programmed to provide one or more of continuity testing at the second interface, testing the first diagnostic tool, or testing the wafer-level IC device.

9. The diagnostic tool of claim 1, further comprising:

a second diagnostic tool comprising;

a dedicated IC testing device including a plurality of contact pads configured to form an electrical interconnect with proximal ends of the probe members in the wafer probe at a second interface;

a second compliant printed circuit electrically coupled to the dedicated IC device;

a plurality of printed conductive traces coupled to the plurality of contact pads on the dedicated IC testing device; and

a plurality of electrical devices printed on the second compliant printed circuit at a position external to the second interface, the electrical devices electrically coupled to the conductive traces on the second compliant printed circuit and configured to provide one or more of continuity testing at the second interface, functionality testing of the first diagnostic tool, or functionality testing of the wafer-level IC device.

10. The diagnostic tool of claim 9, further comprising an electrical connection between the first diagnostic tool and the second diagnostic tool.

11. A diagnostic system for testing a wafer-level IC device coupled to testing electronics, the diagnostic system comprising:

a first diagnostic tool comprising;

a dedicated IC testing device including a plurality of contact pads;

a first compliant printed circuit comprising a flexible polymeric sheet located at a first interface between the dedicated IC testing device and a wafer probe, the first compliant printed circuit comprising a plurality of contact pads electrically coupled to the contact pads on the dedicated IC testing device and contact pads contacting proximal ends of probe members in the wafer probe;

a plurality of printed conductive traces electrically coupled to the plurality of the contact pads of the first compliant printed circuit; and

a plurality of electrical devices printed on the first compliant printed circuit at a position away from the first interface, the electrical devices electrically coupled to the conductive traces and configured to provide one or more of continuity testing at the first interface, continuity testing at a second interface between distal ends of the probe members in the wafer probe and the wafer-level IC device, or functionality testing of the wafer-level IC device.

12. The diagnostic system of claim 11, wherein the electrical devices comprise at least one of a capacitor, a resistor, a filter, a signal or power altering and enhancing device, a capacitive coupling feature, a memory device, an embedded integrated circuit, and a RF antennae.

13. The diagnostic system of claim 11, wherein the first compliant printed circuit comprises one or more printed layers comprising one or more of a dielectric layer, a ground plane, or a power plane.

14. The diagnostic system of claim 11, further comprising:

a second diagnostic tool comprising;

a second compliant printed circuit comprising a plurality of contact pads configured to form an electrical interconnect with distal ends of probe members in the wafer probe and contact pads on the wafer-level IC device at a second interface;

a plurality of printed conductive traces electrically coupled to the plurality of the contact pads on the second compliant printed circuit; and

a plurality of electrical devices printed on the second compliant printed circuit at a position away from the second interface, the electrical devices electrically coupled to the conductive traces on the second compliant printed circuit and adapted to provide one or more of continuity testing at the second interface or functionality testing of the wafer-level IC device.

15. The diagnostic system of claim 14, further comprising an electrical connection between the first diagnostic tool and the second diagnostic tool.

16. A method of making a first diagnostic tool for testing a wafer-level IC device coupled to testing electronics by a wafer probe, the method comprising the steps of:

printing a plurality of contact pads on a first compliant printed circuit comprising a flexible polymeric sheet, the contact pads contacting distal ends of probe members in the wafer probe and-raised probe members located on the compliant printed circuit in an array contacting a plurality of contact pads on the wafer-level IC device at a first interface;

printing a plurality of conductive traces electrically coupled to the plurality of contact pads on the first compliant printed circuit;

printing a plurality of electrical devices on the first compliant printed circuit at a location external to the first interface and in a manner such that the electrical devices are electrically coupled to the conductive traces;

positioning the first compliant printed circuit between the wafer probe and the wafer-level IC device to form an electrical interconnect at the first interface; and

evaluating one or more of continuity at the first interface or functionality of one or more wafer-level IC devices.

17. The method of claim 16, wherein the conductive traces comprise substantially rectangular cross-sectional shapes.

18. The method of claim 16, further comprising printing a conductive material, a non-conductive material, and a semi-conductive material on a single layer of the compliant printed circuit.

19. The method of claim 16, further comprising printing one or more of a capacitor, a resistor, a filter, a signal or power altering and enhancing device, a capacitive coupling feature, a memory device, an embedded integrated circuit, and a RF antennae on the first compliant printed circuit.

20. The method of claim 16, further comprising printing one or more of a dielectric layer, a ground plane, or a power plane on the first compliant printed circuit.

21. The method of claim 16, further comprising a method of making a second diagnostic tool, the method comprising the steps of:

forming an electrical interconnect with proximal ends of the probe members and contact pads on a dedicated IC testing device at a second interface;

electrically coupling the dedicated IC testing device with a second compliant printed circuit;

printing a plurality of conductive traces to be electrically coupled to the dedicated IC device;

printing a plurality of electrical devices on the second compliant printed circuit at a position away from the second interface and such that the electrical devices are electrically coupled to the conductive traces on the second compliant printed circuit; and

evaluating one or more of continuity at the second interface, functionality of the first diagnostic tool, or functionality of the wafer-level IC device.