High speed multiple memory interface I/O cell

• US 8,912,818 B2
• Filed: 10/30/2012
• Issued: 12/16/2014
• Est. Priority Date: 10/09/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Bhakta, Dharmesh, Lim, Hong-Him, Kong, Cheng-Gang, Randazzo, Todd
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US13/663,753
• Publication Number:
  US 20130049799A1
• Time in Patent Office: 777 Days
• Field of Search: 326/26, 326/30, 326 81- 83, 326 86- 87, 327108-109
• US Class Current: 326/30
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Claims

1. A calibration circuit comprising:

an amplifier having a first input, a second input, and an output, wherein said first input receives a reference signal and said second input is configured to connect to an external reference component;

a current steering digital-to-analog converter (DAC) having a first input, a first analog output, and a second analog output, wherein said first input is connected to the output of said amplifier and said first analog output is connected to the second input of said amplifier;

a comparator having a first input receiving said reference signal, a second input connected to said second analog output of said current steering DAC, and an output at which an output of said calibration circuit is presented;

a slew calibration network connected to said second input of said comparator and configured to adjust a slew rate of said calibration circuit; and

an on-die termination (ODT) network connected to said second input of said comparator.

2. The calibration circuit according to claim 1, wherein said calibration circuit is configured to provide wide-range fine-granularity calibration of one or more driver impedances.

3. The calibration circuit according to claim 1, wherein said calibration circuit is configured to provide wide-range fine-granularity calibration of one or more on-die termination impedances.

4. The calibration circuit according to claim 1, wherein said calibration circuit is configured to calibrate impedances to within 5% of a target value.

5. The calibration circuit according to claim 1, wherein said slew calibration network comprises:

a plurality of first cascode pairs connected to said second input of said comparator and configured to adjust a slew rate of a p-channel; and

a plurality of second cascode pairs connected to said second input of said comparator and configured to adjust a slew rate of an n-channel.

6. The calibration circuit according to claim 5, wherein each of said plurality of first cascode pairs and said plurality of second cascode pairs comprise transistor only cascode pairs.

7. The calibration circuit according to claim 1, wherein said slew calibration network provides 7 bits of slew calibration.

8. The calibration circuit according to claim 1, wherein ODT calibration network comprises:

a p-channel ODT network connected to said second input of said comparator; and

an n-channel ODT network connected to said second input of said comparator.

9. The calibration circuit according to claim 8, wherein said ODT calibration network is configured to provide 7 bits of ODT calibration.

10. The calibration circuit according to claim 9, wherein:

a least significant bit of said p-channel ODT network comprises eight series transistors and sixteen series resistors; and

a least significant bit of said n-channel ODT network comprises eight series transistors and sixteen series resistors.

11. The calibration circuit according to claim 9, wherein said ODT calibration network comprises a plurality of reference segments configured to provide a respective weight for each bit in a range from one-sixteenth to four, inclusive.

12. The calibration circuit according to claim 1, wherein said current steering DAC comprises:

a first transistor having a first size and connected to said first output; and

a plurality of second transistors having a second size and connected to said second output, wherein said first size is substantially larger than said second size.

13. The calibration circuit according to claim 12, wherein said first size is more than forty times said second size.

14. The calibration circuit according to claim 1, wherein said calibration circuit is configured to calibrate an impedance of an input/output (I/O) cell of a memory circuit.

15. The calibration circuit according to claim 14, wherein said calibration circuit is coupled to an impedance controller module of said memory circuit.

16. The calibration circuit according to claim 14, wherein said I/O cell is configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

17. The calibration circuit according to claim 14, wherein said ODT network replicates one or more portions of pad ODT networks of said I/O cell.

18. The calibration circuit according to claim 11, wherein said plurality of reference segments comprises:

one or more first reference segments, each having a first impedance;

one or more second reference segments, each having a second impedance;

a third reference segment having a third impedance;

a fourth reference segment having a fourth impedance; and

a fifth reference segment having a fifth impedance.

19. The calibration circuit according to claim 18, wherein said first, second, third, fourth, and fifth impedances are related by powers of 2.

20. The calibration circuit according to claim 1, wherein said external reference component comprises a resistor.