Semiconductor integrated circuit

• US 8,912,822 B2
• Filed: 01/29/2013
• Issued: 12/16/2014
• Est. Priority Date: 03/27/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yasuda, Shinichi, Oda, Masato, Fujita, Shinobu
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/753,091
• Publication Number:
  US 20130257477A1
• Time in Patent Office: 686 Days
• Field of Search: None
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories.

Claims

1. A semiconductor integrated circuit, comprising:

a plurality of input wires comprising;

a first input wire; and

a second input wire;

a first look-up table (LUT) comprising;

a first memory group comprising a plurality of first memories;

a first output terminal; and

a first multiplexer comprising a first number of first switches connected to the first input wire and a second number of second switches connected to the second input wire, the second number being less than the first number, the first multiplexer being configured to transfer information from one of the first memories to the first output terminal according to signals input from the input wires; and

a second LUT comprising;

a second memory group comprising a plurality of second memories;

a second output terminal; and

a second multiplexer comprising a third number of third switches connected to the second input wire and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second multiplexer being configured to transfer information from one of the second memories to the second output terminal according to the signals input from the input wires.

2. The semiconductor integrated circuit of claim 1, further comprising:

a third multiplexer configured to select the information output from the first output terminal of the first LUT and the information output from the second output terminal of the second LUT.

3. The semiconductor integrated circuit of claim 2, further comprising:

a third output terminal configured to output the information selected by the third multiplexer;

a fourth output terminal configured to output the information output from the first multiplexer of the first LUT; and

a fifth output terminal configured to output the information output from the second multiplexer of the second LUT.

4. The semiconductor integrated circuit of claim 1,

wherein the second number is 2.

5. The semiconductor integrated circuit of claim 1,

wherein the first LUT is connected to N input wires including the first input wire and the second input wire, and

wherein the second LUT is connected to M input wires including the first input wire and the second input wire (M<

N).

6. The semiconductor integrated circuit of claim 1, further comprising:

a first power-supply-control switch provided between a power-supply/ground wire and the first memory group; and

a second power-supply-control switch provided between the power-supply/ground wire and the second memory group.

7. The semiconductor integrated circuit of claim 6, further comprising:

a first power-supply-control memory connected to the first power-supply-control switch; and

a second power-supply-control memory connected to the second power-supply-control switch,

wherein each of the first and second memories is a nonvolatile memory, and

wherein the first and second power-supply-control switches are controlled according to information stored in the first and second power-supply-control memories, respectively.

8. The semiconductor integrated circuit of claim 1,

wherein each of the first and second memories is a nonvolatile memory.

9. The semiconductor integrated circuit of claim 1, further comprising:

a first power-supply-control switch provided between a power-supply/ground wire and a first part of the first memories and between the power-supply/ground wire and a first part of the second memories;

a second power-supply-control switch provided between the power-supply/ground wire and a second part of the first memories and between the power-supply/ground wire and a second part of the second memories;

wherein each of the first and second memories is a nonvolatile memory, and

wherein the first and second power-supply-control switches are complementarily controlled.

10. The semiconductor integrated circuit of claim 9

wherein the input wires further comprises a third input wire connected to the first and second power-supply-control switches,

wherein the first and second power-supply-control switches are complementarily controlled according to a signal input from the third input wire.

11. The semiconductor integrated circuit of claim 9, further comprising:

a plurality of third input wires connected to each of the first and second power-supply-control switches,

wherein the first and second power-supply-control switches are complementarily controlled according to signals input from the third input wires.

12. A semiconductor integrated circuit, comprising:

first to Nth input wires, N being an integer larger than 1;

a first look-up table (LUT) comprising;

a first memory group comprising 2^N memories;

a first output terminal; and

a first multiplexer comprising first to N-th stage switch groups, the first stage switch group being connected to the first memory group, the N-th stage switch group being connected to the first output terminal, the i-th stage switch group comprising 2(^N-i+1) switches and being controlled by a signal input from the i-th input wire, i being integer ranging from 1 to N; and

a second LUT comprising;

a second memory group comprising 2^N memories;

a second output terminal; and

a second multiplexer comprising first to N-th stage switch groups, the first stage switch group being connected to the second memory group, the N-th stage switch group being connected to the second output terminal, the i-th stage switch group comprising 2(^N-i+1) switches and being controlled by the signal input from the (N-i+1)-th input wire.

13. A semiconductor integrated circuit, comprising:

a plurality of input wires;

a memory group comprising a plurality of non-volatile memories;

a first power-supply-control switch provided between a power-supply/ground wire and a part of the non-volatile memories and controlled with a signal input from one of the input wires;

a second power-supply-control switch provided between the power-supply/ground wire and the other part of the non-volatile memories and controlled with the signal input from the one of the input wires; and

a switch group connected to the non-volatile memories and controlled with a signal input from the other of the input wires.