EL display panel, power supply line drive apparatus, and electronic device
First Claim
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1. An electroluminescence display device comprising a plurality of pixel circuits and a pixel driving circuit,wherein each of the plurality of pixel circuits includes an electroluminescence element, andwherein in a layout pattern of the pixel driving circuit:
- an output line is electrically directly connected to a first source/drain region of a first transistor of a buffer circuit and a first source/drain region of a second transistor of the buffer circuit, a row of pixel circuits being electrically directly connected to said output line;
a different output line is electrically directly connected to a first source/drain region of a third transistor of a different buffer circuit and a first source/drain region of a fourth transistor of the different buffer circuit, a different row of pixel circuits being electrically directly connected to said different output line;
a high-potential power supply line is electrically directly connected a second source/drain region of the first transistor to a second source/drain region of the third transistor, said high-potential power supply line not crossing said output line or said different output line;
a low-potential power supply line is electrically directly connected a second source/drain region of the second transistor to a second source/drain region of the fourth transistor, said low-potential power supply line not crossing said output line or said different output line,wherein the high-potential power supply line and the low-potential power supply line are extending in a column direction, andwherein the high-potential power supply line and the low-potential power supply line are disposed on an input side of the buffer circuit.
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Abstract
Disclosed herein is an electroluminescence display panel including a pixel circuit, a signal line, a scan line, a drive power supply line, a common power supply line, a power supply line drive circuit, a high-potential power supply line, and a low-potential power supply line.
26 Citations
11 Claims
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1. An electroluminescence display device comprising a plurality of pixel circuits and a pixel driving circuit,
wherein each of the plurality of pixel circuits includes an electroluminescence element, and wherein in a layout pattern of the pixel driving circuit: -
an output line is electrically directly connected to a first source/drain region of a first transistor of a buffer circuit and a first source/drain region of a second transistor of the buffer circuit, a row of pixel circuits being electrically directly connected to said output line; a different output line is electrically directly connected to a first source/drain region of a third transistor of a different buffer circuit and a first source/drain region of a fourth transistor of the different buffer circuit, a different row of pixel circuits being electrically directly connected to said different output line; a high-potential power supply line is electrically directly connected a second source/drain region of the first transistor to a second source/drain region of the third transistor, said high-potential power supply line not crossing said output line or said different output line; a low-potential power supply line is electrically directly connected a second source/drain region of the second transistor to a second source/drain region of the fourth transistor, said low-potential power supply line not crossing said output line or said different output line, wherein the high-potential power supply line and the low-potential power supply line are extending in a column direction, and wherein the high-potential power supply line and the low-potential power supply line are disposed on an input side of the buffer circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electroluminescence display device comprising a plurality of pixel circuits and a pixel driving circuit,
wherein each of the plurality of pixel circuits includes an electroluminescence element, and wherein in a layout pattern of the pixel driving circuit: -
an output line is electrically directly connected to a first source/drain region of a first transistor of a buffer circuit and a first source/drain region of a second transistor of the buffer circuit, a row of pixel circuits being electrically directly connected to said output line; a different output line is electrically directly connected to a first source/drain region of a third transistor of a different buffer circuit and a first source/drain region of a fourth transistor of the different buffer circuit, a different row of pixel circuits being electrically directly connected to said different output line; a first supply line is electrically directly connected a second source/drain region of the first transistor to a second source/drain region of the third transistor, said first supply line not crossing said output line or said different output line; a second supply line is electrically directly connected a second source/drain region of the second transistor to a second source/drain region of the fourth transistor, said second supply line not crossing said output line or said different output line, wherein the first supply line and the second supply line are extending in a column direction, and wherein a gate electrode of the first transistor and a gate electrode of the third transistor overlap the first supply line and the second supply line. - View Dependent Claims (8, 9, 10, 11)
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Specification
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Current AssigneeSony Corporation (Sony Group Corp.)
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Original AssigneeSony Corporation (Sony Group Corp.)
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InventorsTomida, Masatsugu, Asano, Mitsuru
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Primary Examiner(s)SHERMAN, STEPHEN G
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Application NumberUS14/269,644Publication NumberTime in Patent Office225 DaysField of Search345 76- 83, 345/204, 315/169.3US Class Current345/76CPC Class CodesG09G 2300/0426 Layout of electrodes and co...G09G 2300/0819 used for counteracting unde...G09G 2300/0842 forming a memory circuit, e...G09G 2300/0866 by means of changes in the ...G09G 2310/0256 with the purpose of reversi...G09G 2310/0286 Details of a shift register...G09G 2310/08 Details of timing specific ...G09G 2320/043 Preventing or counteracting...G09G 2320/045 Compensation of drifts in t...G09G 2330/02 Details of power systems an...G09G 2330/021 Power management, e.g. powe...G09G 3/30 using electroluminescent pa...G09G 3/3233 with pixel circuitry contro...G09G 3/3266 Details of drivers for scan...G09G 3/3275 Details of drivers for data...H10K 59/131 Interconnections, e.g. wiri...
