Digital camera with quad core processor
First Claim
Patent Images
1. A device with image capture capability, comprising:
- an image sensor for sensing image data; and
a central processor integrated into a single chip, the central processor comprising;
a plurality of processing units configured to receive at least a portion of the sensed image data via a connection to the image sensor, and to simultaneously process the portion of the sensed image data, wherein the plurality of processing units are interconnected to each other separately from the connection to the image sensor;
an image sensor interface connecting the image sensor to the plurality of processing units;
an input FIFO (first in, first out) configured to receive data from the image sensor interface and input the data to the plurality of processing units, and an output FIFO configured to receive data processed by the plurality of processing units;
a central processing unit and a data bus connecting the central processing unit to the input FIFO, the central processing unit providing a processing core to operatively control the plurality of processing units;
a data cache connected to the plurality of processing units to store the data processed by the plurality of processing units until required by the central processing unit; and
a plurality of interfaces for transmitting the data processed by the plurality of processing units to functional components within the device, each of the plurality of interfaces being connected to the data cache for reading the data processed by the plurality of processing units,wherein each processing unit of the plurality of processing units includes at least one address generator for addressing processed data for transmission to the functional components.
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Abstract
A digital camera that has a CMOS image sensor and a central processor. The central processor has four processing units and an image sensor interface integrated onto a single chip. The image sensor interface receives data from the CMOS image sensor and the four processing units simultaneously process the data.
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Citations
9 Claims
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1. A device with image capture capability, comprising:
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an image sensor for sensing image data; and a central processor integrated into a single chip, the central processor comprising; a plurality of processing units configured to receive at least a portion of the sensed image data via a connection to the image sensor, and to simultaneously process the portion of the sensed image data, wherein the plurality of processing units are interconnected to each other separately from the connection to the image sensor; an image sensor interface connecting the image sensor to the plurality of processing units; an input FIFO (first in, first out) configured to receive data from the image sensor interface and input the data to the plurality of processing units, and an output FIFO configured to receive data processed by the plurality of processing units; a central processing unit and a data bus connecting the central processing unit to the input FIFO, the central processing unit providing a processing core to operatively control the plurality of processing units; a data cache connected to the plurality of processing units to store the data processed by the plurality of processing units until required by the central processing unit; and a plurality of interfaces for transmitting the data processed by the plurality of processing units to functional components within the device, each of the plurality of interfaces being connected to the data cache for reading the data processed by the plurality of processing units, wherein each processing unit of the plurality of processing units includes at least one address generator for addressing processed data for transmission to the functional components. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification