Memory system with sectional data lines

• US 8,913,413 B2
• Filed: 01/31/2012
• Issued: 12/16/2014
• Est. Priority Date: 08/25/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Yan, Tianhong, Fasoli, Luca
• Primary Examiner(s): Norman, James G
• Application Number:
  US13/362,311
• Publication Number:
  US 20120170346A1
• Time in Patent Office: 1,050 Days
• Field of Search: None
• US Class Current: 365/51
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

Claims

1. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements arranged in groups;

bit lines in communication with the non-volatile storage elements;

multiple sets of first local data lines, each group includes its own set of first local data lines;

multiple sets of second local data lines, each group includes its own set of second local data lines;

each set of first local data lines and each set of second local data lines being respectively outside the plurality of non-volatile storage elements for its respective group;

a set of global data lines outside the plurality of non-volatile storage elements arranged in groups;

first selection circuits, each group includes a different subset of the first selection circuits for selectively electrically connecting a subset of the bit lines to first local data lines for the respective group or second local data lines for the respective group;

second selection circuits, the second selection circuits selectively electrically connect a subset of the set of first local data lines for the respective group or a subset of the set of second local data lines for the respective group to the global data lines; and

control circuits in communication with the global data lines.

2. A non-volatile storage device according to claim 1, wherein:

the plurality of non-volatile storage elements is a three-dimensional memory array that includes multiple layers of memory cells;

the control circuits comprise column control circuitry that includes sense amplifiers;

the first selection circuits include pmos transistors connected to nmos transistors;

the second selection circuits includes 2;

1 multiplexers; and

the groups are blocks of memory cells that share a common set of sense amplifiers.

3. A non-volatile storage device according to claim 1, wherein:

the second selection circuits are 4;

1 multiplexers.

4. A non-volatile storage device according to claim 1, wherein:

the first local data lines are positioned in at least one metal layer below the plurality of non-volatile storage elements; and

the global data lines are positioned in at least one metal layer above the plurality of non-volatile storage elements.

5. The non-volatile storage device of claim 1, further comprising:

a substrate, the control circuits in communication with the global data lines, being positioned on the substrate.

6. The non-volatile storage device of claim 5, further comprising:

the sets of first local data lines and the sets of second local data lines being positioned between the substrate and the non-volatile storage elements.

7. The non-volatile storage device of claim 1, further comprising:

the global data lines are positioned outside of the plurality of non-volatile storage elements arranged in groups.

8. The non-volatile storage device of claim 1 further comprising:

the non-volatile storage elements are arranged in three-dimensions.

9. The non-volatile storage device of claim 1 further comprising:

the non-volatile storage elements are arranged in a monolithic three-dimensional memory structure.

10. The non-volatile storage device of claim 1 further comprising:

the non-volatile storage device includes a three-dimensional memory array including the non-volatile storage elements.

11. A method for operating a data storage system, comprising:

selecting a first bay from a plurality of bays, the plurality of bays comprise an array of data storage elements, each bay includes a plurality of blocks of data storage elements and multiple sets of local data lines, each block includes a set of local data lines outside the data storage elements;

selecting a block within the first bay, the selected block includes multiple columns of first selection circuits for selective communication of bit lines with the set of local data lines for the respective block, each of the first selection circuits are connected to a different bit line for the selected block, the bit lines for the selected block are in communication with data storage elements, and the selected block includes second selection circuits providing selective communication of the set of local data lines with a set of global data lines, the set of global data lines being outside the plurality of blocks of data storage elements;

selecting a column of the selected block and using the first selection circuits of the selected column to provide selective communication between a subset of the set of local data lines for the respective block and a subset of bit lines connected to the first selection circuits of the selected column;

selecting the subset of the local data lines for the respective block to communicate with the set of global data lines using the second selection circuits, the set of global data lines also connect to local data lines for other blocks; and

performing a memory operation, using the global data lines, on data storage elements in communication with the selected subset of local data lines.

12. The method of claim 11, further comprising:

driving signals on global data lines;

selecting one or more word lines; and

driving signals on the selected one or more word lines for the memory operation.

13. The method of claim 11, wherein:

the local data lines are in at least one metal layer below the data storage elements; and

the global data lines are in at least one metal layer above the data storage elements.

14. The method of claim 11 further comprising:

the array of data storage elements is a three-dimensional memory array.

15. A method for operating a data storage system, comprising:

selectively electrically connecting a subset of bit lines to a subset of a set of local data lines for selective communication of the subset of bit lines with the subset of the set of local data lines using a set of first selection circuits, the subset of bit lines are also in communication with a first subset of a plurality of data storage elements, the set of local data lines are positioned outside of the plurality of data storage elements;

selecting and electrically connecting the subset of the set of local data lines to a set of global data lines using a set of second selection circuits so that the subset of the set of local data lines are in communication with the set of global data lines, the global data lines are positioned outside of the plurality of data storage elements, the global data lines are connected to control circuitry, the global data lines are also connected to other sets of local data lines by the set of second selection circuits; and

performing a memory operation on at least a portion of the first subset of data storage elements using the control circuitry.

16. The method of claim 15, wherein:

the plurality of data storage elements comprise a monolithic three-dimensional memory array;

the sets of local data lines are in at least one metal layer below the monolithic three-dimensional memory array; and

the global data lines are in at least one metal layer above the monolithic three-dimensional memory array.

17. The method of claim 15, wherein:

the selectively electrically connecting the subset of bit lines to the subset of the set of local data lines comprises sending selection signals to the set of first selection circuits connected to the subset of bit lines and the set of local data lines; and

the selecting and electrically connecting the subset of the set of local data lines to the set of global data lines using a set of second selection circuits comprises sending selection signals to multiplexer circuits connected to the set of local data lines and the set of global data lines.

18. The method of claim 15 further comprising:

the data storage elements are arranged in three-dimensions.

19. The method of claim 15 further comprising:

the data storage elements are arranged in a three-dimensional memory structure.

20. The method of claim 15 further comprising:

the data storage system includes a three-dimensional memory array including the data storage elements.