Video decoding system having a programmable variable-length decoder

• US 8,913,667 B2
• Filed: 04/01/2003
• Issued: 12/16/2014
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hsiun, Vivian, MacInnis, Alexander G., Xie, Xiaodong
• Primary Examiner(s): Rao, Andy
• Application Number:
  US10/404,387
• Publication Number:
  US 20040028141A1
• Time in Patent Office: 4,277 Days
• Field of Search: 37524001-24029
• US Class Current: 375/240.23
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/129 Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
• CPC Class Codes: H04N 19/15 by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
• CPC Class Codes: H04N 19/157 Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/60 : using transform coding
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/70 : characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/82 : involving filtering within a prediction loop
• CPC Class Codes: H04N 19/90 : using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• CPC Class Codes: H04N 19/91 : Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

Video decoding system having a programmable variable-length decoding accelerator. The system includes a decoder processor and a variable-length decoding accelerator. The variable-length decoding accelerator is coupled to the decoder processor and performs variable-length decoding operations on variable-length code in the video data stream. The variable-length decoding accelerator is capable of decoding variable-length code according to any of a plurality of decoding methods. In one embodiment, the variable-length decoder includes a plurality of code tables stored in memory and a code table selection register that is programmable to dictate which of the plurality of code tables is to be utilized to decode variable-length code. In one embodiment, the decoding system includes two variable-length decoding accelerators.

Claims

1. A video decoding system comprising:

a decoder processor configured to perform decoding functions on a video data stream;

a first variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on macroblock data elements in the video data stream, each macroblock data element representing a macroblock of a video frame, each macroblock data element comprising a macroblock header and coefficient data;

a second variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on macroblock data elements in the video data stream; and

wherein the first and second variable-length decoding accelerators are configured to alternately decode macroblock data elements in the video data stream such that the first variable-length decoding accelerator decodes a macroblock header of one macroblock data element while the second variable-length decoding accelerator decodes coefficient data of another macroblock data element during a first stage of decoding, and the second variable-length decoding accelerator decodes a macroblock header of one macroblock data element while the first variable-length decoding accelerator decodes coefficient data of another macroblock data element during a second stage of decoding.

2. The system of claim 1, wherein each of the variable-length decoding accelerators is configured to decode the macroblock header of each macroblock data element before decoding the coefficient data of the macroblock data element.

3. The system of claim 1, wherein the variable-length decoding accelerators are configured such that the decoding of successive macroblock data elements in the data stream is initiated during corresponding successive variable time periods.

4. The system of claim 3, wherein the variable-length decoding accelerators are configured such that the decoding of each macroblock data element in the data stream is completed before an end of the variable time period that follows the variable time period in which decoding of that macroblock data element was initiated.

5. A video decoding system comprising:

a decoder processor configured to perform decoding functions on a video data stream;

a first variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on variable-length code in the video data stream, wherein the first variable-length decoding accelerator is configured by the decoder processor to decode variable-length codes according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the variable video data stream, wherein the first variable-length decoding accelerator is configured to use for the selected decoding format a variable-length coding table of a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats; and

a second variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on variable-length code in the video data stream.

6. The system of claim 5, wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information.

7. The system of claim 5, wherein the first variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode a variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed.

8. The system of claim 5, wherein the second variable-length decoding accelerator is hard-wired to decode a variable-length code according to a particular decoding method.

9. The system of claim 5, wherein the second variable-length decoding accelerator is configured to decode a variable-length code according to any of the plurality of different decoding formats.

23. The system of claim 5, wherein the plurality of different decoding formats correspond to different compression algorithms.

10. A video decoding system comprising:

a decoder processor configured to perform decoding functions on a video data

 

stream;

a variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on a variable-length code in the video data stream;

wherein the variable-length decoding accelerator is configured by the decoder processor to decode a variable-length code according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the video data stream; and

wherein the variable-length decoding accelerator is configured to use for the selected decoding format a variable-length coding table of a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats.

11. The system of claim 10 wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information.

12. The system of claim 10, wherein the variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode the variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed.

24. The system of claim 10, wherein the plurality of different decoding formats correspond to different discrete cosine transform (DCT)-based compression standards.

13. A video decoding system comprising:

a decoder processor configured to perform decoding functions on a video data stream; and

a hardware variable-length decoding accelerator external to the decoder processor and coupled to the decoder processor and configured to perform variable-length decoding operations on a variable-length code in the video data stream, wherein the variable-length decoding accelerator is configurable by the decoder processor to decode variable-length codes according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the video data stream, wherein the hardware variable-length decoding accelerator includes a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats.

14. The system of claim 13, wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information.

15. The system of claim 13, wherein the variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode the variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed.

16. A method, comprising:

receiving, by a first variable-length decoding accelerator, a first macroblock data element in a video data stream from a decoder processor, the first macroblock data element comprising a first macroblock header and first coefficient data;

receiving, by a second variable-length decoding accelerator, a second macroblock data element in the video data stream from the decoder processor, the second macroblock data element comprising a second macroblock header and second coefficient data;

decoding, by the second variable-length decoding accelerator during a stage of decoding, the second coefficient data after decoding the second macroblock header; and

decoding, by the first variable-length decoding accelerator during the stage of decoding, the first macroblock header while the second variable-length decoding accelerator decodes the second coefficient data.

17. The method of claim 16, further comprising:

receiving, by the second variable-length decoding accelerator, a third macroblock data element in the video data stream from the decoder processor, the third macroblock data element comprising a third macroblock header and third coefficient data;

decoding, by the first variable-length decoding accelerator, the first coefficient data after decoding the first macroblock header; and

decoding, by the second variable-length decoding accelerator, the third macroblock header while the first variable-length decoding accelerator decodes the first coefficient data.

18. The method of claim 16, wherein each macroblock data element represents a macroblock of a video frame.

19. The method of claim 16, further comprising performing, by the decoder processor, decoding functions on the video data stream.

20. A method, comprising:

receiving, by a video processing system, video data of a first coding format;

configuring, by a decoder processor, a variable-length decoding accelerator of the video processing system to use a first variable-length coding table based at least in part on the first coding format;

decoding the video data of the first coding format by the variable-length decoding accelerator;

receiving, by the video processing system, video data of a second coding format differing from the first coding format;

configuring, by the decoder processor, the variable-length decoding accelerator to use a second variable length coding table that is different from the first variable-length coding table based at least in part on the second coding format; and

decoding the video data of the second coding format by the variable-length decoding accelerator.

21. The method of claim 20, wherein configuring the variable-length decoding accelerator of the video processing system to use the first variable-length coding table further comprises setting a first value in a coding table selection register, the first value indicating the first variable-length coding table.

22. The method of claim 20, wherein the first coding format and the second coding format correspond to different discrete cosine transform (DCT)-based, variable-length coded, block-motion-compensated compression algorithms.