Optimizing write and wear performance for a memory

• US 8,914,557 B2
• Filed: 12/16/2005
• Issued: 12/16/2014
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Fortin, Michael R., Reinauer, Robert L.
• Primary Examiner(s): Wong, Titus
• Application Number:
  US11/303,382
• Publication Number:
  US 20070162700A1
• Time in Patent Office: 3,287 Days
• Field of Search: 710/29, 711/103
• US Class Current: 710/29
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/305 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

In an example embodiment, data is transferred from a higher speed memory to a lower speed memory or data storage device after determining a size of a block of data to be written to the lower speed memory. In an example embodiment data is collected in the higher speed memory until an amount of collected data is equal to or greater than the size of the block to be written, and then the collected data is transferred to the lower speed memory or data storage. In an example embodiment, the block size can be a predefined erase block size of the lower speed memory. In an example embodiment, the lower speed device is a flash memory.

Claims

1. A computer system comprising:

a higher-speed memory device configured for operating at a higher speed than a lower-speed memory device;

an additional memory device that is configured for operating at a lower-speed than the higher-speed memory device;

the lower-speed memory device configured as removable storage media;

the computer system configured for;

receiving data designated to be stored on the lower-speed memory device;

testing the lower-speed memory device to determine a preferred write size of the lower-speed memory device;

storing on the higher-speed memory device an amount of the received data that matches the preferred write size of the lower-speed memory device;

backing-up the amount of the stored data to the additional memory device;

writing the amount of the stored data to the lower-speed memory device in response to the storing and to a period of low activity of the computer system.

2. The computer system of claim 1, wherein the lower-speed memory device comprises flash memory.

3. The computer system of claim 2, wherein the preferred write size is a preferred erase block size of the flash memory.

4. The computer system of claim 1 further configured for warning that the stored data has not yet been written to the lower-speed memory device in response to the lower-speed memory device being removed from the computer system prior to the stored data being written to the lower-speed memory device.

5. The computer system of claim 1 further configured for presenting an option to write the stored data to the lower-speed memory device.

6. The computer system of claim 1, the writing excluding older duplicate data of duplicate data of the amount of the stored data, where the older duplicate data is older than other duplicates of the duplicate data.

7. The computer system of claim 1 further configured for invalidating, prior to the writing, the amount of the stored data on the higher-speed memory device in response to a previous writing impacting the amount of the stored data.

8. A method comprising:

receiving, by a computing device, data designated to be stored on a lower-speed memory device configured as removable storage media, where the computing device comprises the lower-speed memory device, a higher-speed memory device configured for operating at a higher speed than the lower-speed memory device, and an additional memory device that is configured for operating at a lower-speed than the higher-speed memory device;

testing, by the computing device, the lower-speed memory device to determine a preferred write size of the lower-speed memory device;

storing, by the computing device on the higher-speed memory device, an amount of the received data that matches the preferred write size of the lower-speed memory device;

backing-up, by the computing device, the amount of the stored data to the additional memory device; and

writing, by the computing device, the amount of the stored data to the lower-speed memory device in response to the storing and to a period of low activity of the computer system.

9. The method of claim 8, the writing excluding older duplicate data of duplicate data of the amount of the stored data, where the older duplicate data is older than other duplicates of the duplicate data.

10. The method of claim 8 further comprising invalidating, prior to the writing, the amount of the stored data on the higher-speed memory device in response to a previous writing impacting the amount of the stored data.

11. The method of claim 8, wherein the lower-speed memory device comprises flash memory.

12. The method of claim 8, wherein the preferred write size is a preferred erase block size of the flash memory.

13. The method of claim 8 further comprising presenting an option to write the stored data to the lower-speed memory device.

14. The method of claim 8 further comprising warning that the stored data has not yet been written to the lower-speed memory device in response to the lower-speed memory device being removed from the computer system prior to the stored data being written to the lower-speed memory device.

15. At least one computer storage device storing computer-executable instructions that, when executed by a computing device, cause the computing device to perform a method comprising:

receiving data designated to be stored on a lower-speed memory device configured as removable storage media, where the computing device comprises the lower-speed memory device, a higher-speed memory device configured for operating at a higher speed than the lower-speed memory device, and an additional memory device that is configured for operating at a lower-speed than the higher-speed memory device;

testing the lower-speed memory device to determine a preferred write size of the lower-speed memory device;

storing, on the higher-speed memory device, an amount of the received data that matches the preferred write size of the lower-speed memory device;

backing-up the amount of the stored data to the additional memory device; and

writing the amount of the stored data to the lower-speed memory device in response to the storing and to a period of low activity of the computer system.

16. The method of claim 15, the writing excluding older duplicate data of duplicate data of the stored amount of the received data, where the older duplicate data is older than other duplicates of the duplicate data.

17. The method of claim 15 further comprising invalidating, prior to the writing, the amount of the stored data on the higher-speed memory device in response to a previous writing impacting the amount of the stored data.

18. The method of claim 15, wherein the lower-speed memory device comprises flash memory.

19. The method of claim 15, wherein the preferred write size is a preferred erase block size of the flash memory.

20. The method of claim 15 further comprising warning that the stored data has not yet been written to the lower-speed memory device in response to the lower-speed memory device being removed from the computer system prior to the stored data being written to the lower-speed memory device.