Hybrid memory architectures
First Claim
Patent Images
1. A system having an integrated circuit (IC) package, the system comprising:
- a processing core disposed within the IC package, the processing core having at least a first Double Data Rate (DDR) channel and a second DDR channel;
a hybrid memory module coupled with the first DDR channel, the hybrid memory module comprising;
a volatile memory coupled with the processing core via an internal interface within the IC package, the volatile memory to operate as a last-level hardware managed cache memory with cache misses to be serviced by external memory, wherein if requested data is found in the hybrid memory module a cache hit condition exists and if the requested data is not found in the hybrid memory module a cache miss condition exists; and
a non-volatile memory coupled with the processing core via the internal interface within the IC package, the non-volatile memory to operate as a disk cache to offset memory capacity and bandwidth corresponding to a dual-inline memory module (DIMM) for the DDR channel;
a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component via the second DDR channel, wherein the external memory is external to the hybrid memory module and the external memory is to be searched for the requested data if a cache miss condition exists.
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Abstract
Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.
31 Citations
20 Claims
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1. A system having an integrated circuit (IC) package, the system comprising:
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a processing core disposed within the IC package, the processing core having at least a first Double Data Rate (DDR) channel and a second DDR channel; a hybrid memory module coupled with the first DDR channel, the hybrid memory module comprising; a volatile memory coupled with the processing core via an internal interface within the IC package, the volatile memory to operate as a last-level hardware managed cache memory with cache misses to be serviced by external memory, wherein if requested data is found in the hybrid memory module a cache hit condition exists and if the requested data is not found in the hybrid memory module a cache miss condition exists; and a non-volatile memory coupled with the processing core via the internal interface within the IC package, the non-volatile memory to operate as a disk cache to offset memory capacity and bandwidth corresponding to a dual-inline memory module (DIMM) for the DDR channel; a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component via the second DDR channel, wherein the external memory is external to the hybrid memory module and the external memory is to be searched for the requested data if a cache miss condition exists. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A processing system having comprising:
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a processing core disposed within a first IC package, the processing core having at least a first Double Data Rate (DDR) channel and a second DDR channel; a hybrid memory module coupled with the first DDR channel, the hybrid memory module comprising; a volatile memory coupled with the processing core via an internal interface within the IC package, the volatile memory to operate as a last-level hardware managed cache memory with cache misses to be serviced by external memory, wherein if requested data is found in the hybrid memory module a cache hit condition exists and if the requested data is not found in the hybrid memory module a cache miss condition exists; and a non-volatile memory coupled with the processing core via the internal interface within the IC package, the non-volatile memory to operate as a disk cache to offset memory capacity and bandwidth corresponding to a dual-inline memory module (DIMM) for the DDR channel; a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component via the second DDR channel, wherein the external memory is external to the hybrid memory module and the external memory is to be searched for the requested data if a cache miss condition exists. - View Dependent Claims (11, 12, 13, 14)
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15. A method comprising:
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receiving a data request; searching a cache memory disposed on a die having a processor core generating the data request in response to the data request, the processing core having at least a first Double Data Rate (DDR) channel and a second DDR channel; searching a hybrid memory module comprising both volatile and non-volatile memory in response to the requested data not being found in the cache memory, wherein cache misses are serviced by external memory, and if requested data is found in the hybrid memory module a cache hit condition exists and if the requested data is not found in the hybrid memory module a cache miss condition exists, wherein the hybrid memory module offsets memory capacity and memory bandwidth corresponding to a double data rate (DDR) channel and the memory module is external to the die having the processor core generating the data request; and searching an external memory in response to the requested data not being found in the memory module, wherein the memory module is external to the die having the processor core generating the data request and the memory module. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification