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Data processing method and device

  • US 8,914,590 B2
  • Filed: 09/30/2009
  • Issued: 12/16/2014
  • Est. Priority Date: 08/07/2002
  • Status: Active Grant
First Claim
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1. A processor chip comprising:

  • a plurality of processor cores, including at least one processor having a plurality of ALUs;

    a plurality of local memories comprising copies of main memory areas;

    a cache controller controlling at least one of the local memories;

    wherein;

    the processor chip has multi-thread capabilities; and

    the cache controller is adapted to receive prefetch requests during execution of a first thread and to prefetch data during the execution of a second thread;

    wherein the prefetch commands are software instructions generated by a compiler, andat least some of the prefetch requests are burst requests to the cache controller; and

    the burst request comprising a vector stride request.

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