On-chip comparison and response collection tools and techniques

• US 8,914,694 B2
• Filed: 04/08/2013
• Issued: 12/16/2014
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Rajski, Janusz, Tyszer, Jerzy
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US13/858,737
• Publication Number:
  US 20130305107A1
• Time in Patent Office: 617 Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Claims

1. A method, comprising:

using feedback-free compactors, compacting groups of test responses output from corresponding groups of scan chains and thereby generating compacted test responses, each of the compacted test responses being associated with a respective one of the groups of scan chains;

at a first input, receiving masking data for controlling a masking circuit;

at a second input, receiving expected test response data for evaluating the compacted test responses, the masking data and the expected test response data being received simultaneously at the first and second inputs; and

generating one or more error vectors based at least in part on the compacted test responses and the expected test response data.

2. The method of claim 1, further comprising:

generating information about two or more failing test responses, the information including one or more of a test pattern number and a test cycle number.

3. The method of claim 1, wherein the error vectors are generated on a shift-cycle-by-shift-cycle basis.

4. The method of claim 1, wherein each bit of a respective one of the error vectors corresponds to a respective one of the groups of scan chains.

5. A method, comprising:

compacting groups of test responses output from corresponding groups of scan chains and thereby generating compacted test responses, each of the compacted test responses being associated with a respective one of the groups of scan chains;

at a first input, receiving masking data for controlling a masking circuit;

at a second input, receiving expected test response data for evaluating the compacted test responses, the masking data and the expected test response data being received simultaneously at the first and second inputs;

generating one or more error vectors based at least in part on the compacted test responses and the expected test response data;

loading the one or more error vectors into a multiple-input shift register (MISR);

producing one or more compactor signatures in the MISR; and

storing the one or more compactor signatures in one or more computer-readable media.

6. The method of claim 5, further comprising:

generating a list of candidate fault locations according to the one or more compactor signatures; and

storing the list of candidate fault locations on one or more computer-readable media.

7. A method, comprising:

compacting groups of test responses output from corresponding groups of scan chains and thereby generating compacted test responses, each of the compacted test responses being associated with a respective one of the groups of scan chains;

at a first input, receiving masking data for controlling a masking circuit;

at a second input, receiving expected test response data for evaluating the compacted test responses, the masking data and the expected test response data being received simultaneously at the first and second inputs;

generating one or more error vectors based at least in part on the compacted test responses and the expected test response data;

compacting the error vectors in a priority encoder to produce one or more encoded vectors; and

storing the one or more encoded vectors in one or more computer-readable media.

8. The method of claim 7, wherein the priority encoder produces an encoded vector from multiple error vectors input into the encoder over a plurality of shift cycles.

9. The method of claim 8, wherein the priority encoder produces one encoded vector per test pattern.

10. A system, comprising:

means for compacting groups of test responses output from corresponding groups of scan chains;

means for receiving masking data for controlling a masking circuit;

means for receiving expected compacted test response data, the masking data and the expected compacted test response data being received simultaneously;

means for generating one or more error vectors based at least in part on the compacted test responses and the expected compacted test response data;

means for compressing the one or more error vectors to produce one or more encoded vectors; and

means for storing the one or more encoded vectors.