Methods to integrate SONOS into CMOS flow
First Claim
1. A method comprising:
- depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a non-volatile memory (NVM) transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer;
forming a mask exposing source and drain (S/D) regions of the NVM transistor;
etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and
implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor.
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Abstract
Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.
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Citations
20 Claims
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1. A method comprising:
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depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a non-volatile memory (NVM) transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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depositing a dielectric stack in a first region of a substrate, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; depositing a gate layer over the dielectric stack in the first region and over a surface of the substrate in a second region of the substrate not having the dielectric stack deposited thereon; patterning the gate layer to concurrently form a gate of a non-volatile memory (NVM) transistor in the first region and a gate of a complimentary-metal-oxide-silicon (CMOS) transistor in the first region; forming a mask having openings exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through openings in the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor. - View Dependent Claims (15, 16, 17, 18)
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19. A method comprising:
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depositing and patterning a polysilicon gate layer over a substrate to form a gate of a non-volatile memory (NVM) transistor on a dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer, while concurrently forming a gate of a complimentary-metal-oxide-silicon (CMOS) transistor on a gate oxide on the substrate; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and re-oxidizing the polysilicon gate layer; depositing a spacer layer over the gates of the NVM transistor and CMOS transistor and the surface of the substrate, and anisotropically dry-etching the spacer layer to form spacers adjacent sidewalls of the gates; and forming a lightly-doped drain (LDD) mask including openings exposing S/D regions of the NVM transistor and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a LDD adjacent to the gate of the NVM transistor. - View Dependent Claims (20)
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Specification