Methods to integrate SONOS into CMOS flow

• US 8,916,432 B1
• Filed: 06/16/2014
• Issued: 12/23/2014
• Est. Priority Date: 01/21/2014
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ramkumar, Krishnaswamy, Prabhakar, Venkatraman
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US14/305,137
• Time in Patent Office: 190 Days
• Field of Search: 438/216, 438/266, 257/E21.679, 257/E29.309
• US Class Current: 438/216
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.

Claims

1. A method comprising:

depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a non-volatile memory (NVM) transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer;

forming a mask exposing source and drain (S/D) regions of the NVM transistor;

etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and

implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor.

2. The method of claim 1 wherein the charge-trapping layer is a multi-layer charge-trapping layer comprising at least a first charge-trapping layer overlying the tunneling layer and a second charge-trapping layer overlying the first charge-trapping layer, and wherein removing the at least a first portion of the charge-trapping comprises removing the second charge-trapping layer in S/D regions of the NVM transistor.

3. The method of claim 1 wherein etching the dielectric stack comprises thinning the dielectric stack to a thickness that does not adversely impact subsequent implanting of dopants into S/D regions of the NVM transistor.

4. The method of claim 3 wherein etching the dielectric stack comprises thinning the dielectric stack from a thickness of about 175 angstroms (A) to a thickness of from about 30 Å

to about 40 Å

.

5. The method of claim 1 wherein depositing and patterning the gate layer further comprises depositing and patterning the gate layer over a surface of the substrate in an area not having the dielectric stack thereon, to concurrently form a gate of a complimentary metal on silicon (CMOS) transistor.

6. The method of claim 5 further comprising depositing a first spacer layer over the gate of the NVM transistor, the gate of CMOS transistor and the surface of the substrate, and anisotropically etching the first spacer layer to form first spacers adjacent sidewalls of the gates of the NVM transistor and the CMOS transistor.

7. The method of claim 6 wherein depositing and etching the first spacer layer to form first spacers is done prior to forming the mask exposing S/D regions of the NVM transistor.

8. The method of claim 6 further comprising depositing a second spacer layer over the gate of the NVM transistor, the gate of CMOS transistor and the surface of the substrate, and anisotropically etching the second spacer layer to form second spacers (Spacer-2) adjacent the first spacers of the NVM transistor and the CMOS transistor, wherein the second spacer layer comprises silicon nitride (SiN), and wherein etching the second spacer layer comprises removing at least a second of the charge-trapping layer in S/D regions of the NVM transistor.

9. The method of claim 8 wherein the tunneling layer and a second portion of the charge-trapping layer remaining in the S/D regions of the NVM transistor after etching the dielectric stack through the mask to thin the dielectric stack, protects the surface of the substrate in the S/D regions from damage during the forming of the first spacers and the second spacers.

10. The method of claim 1 wherein gate layer comprises polysilicon, and wherein the method further comprises re-oxidizing the polysilicon after depositing and patterning the gate layer over to form a polysilicon gate of the NVM transistor.

11. The method of claim 10 wherein the dielectric stack comprises an oxide-nitride-oxide (ONO) stack and the NVM transistor comprises a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.

12. The method of claim 1 wherein at least one of the tunneling layer or the blocking layer comprises a high-k material.

13. The method of claim 1 wherein the mask formed exposing S/D regions of the NVM transistor prior to thinning the dielectric stack is an LDD mask, and wherein implanting dopants into S/D regions of the NVM transistor comprises implanting through openings in the LDD mask.

14. A method comprising:

depositing a dielectric stack in a first region of a substrate, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer;

depositing a gate layer over the dielectric stack in the first region and over a surface of the substrate in a second region of the substrate not having the dielectric stack deposited thereon;

patterning the gate layer to concurrently form a gate of a non-volatile memory (NVM) transistor in the first region and a gate of a complimentary-metal-oxide-silicon (CMOS) transistor in the first region;

forming a mask having openings exposing source and drain (S/D) regions of the NVM transistor;

etching the dielectric stack through openings in the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and

implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor.

15. The method of claim 14 wherein the charge-trapping layer is a multi-layer charge-trapping layer comprising at least a first charge-trapping layer overlying the tunneling layer and a second charge-trapping layer overlying the first charge-trapping layer, and wherein removing the at least a first portion of the charge-trapping comprises removing the second charge-trapping layer in S/D regions of the NVM transistor.

16. The method of claim 14 wherein gate layer comprises polysilicon, and wherein the method further comprises depositing a spacer layer over the gate of the NVM transistor, the gate of CMOS transistor and the surface of the substrate, and anisotropically etching the spacer layer to form spacers adjacent sidewalls of the gates of the NVM transistor and the CMOS transistor, and re-oxidizing the polysilicon.

17. The method of claim 16 wherein depositing and etching the spacer layer to form spacers, and re-oxidizing the polysilicon is done prior to forming the mask exposing S/D regions of the NVM transistor.

18. The method of claim 16 wherein depositing and etching the spacer layer to form spacers and re-oxidizing the polysilicon is done after implanting dopants into S/D regions of the NVM transistor, and wherein the tunneling layer and a second portion of the charge-trapping layer remaining in the S/D regions of the NVM transistor after etching the dielectric stack through the mask to thin the dielectric stack, protects the surface of the substrate in the S/D regions from damage during the forming of the spacers.

19. A method comprising:

depositing and patterning a polysilicon gate layer over a substrate to form a gate of a non-volatile memory (NVM) transistor on a dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer, while concurrently forming a gate of a complimentary-metal-oxide-silicon (CMOS) transistor on a gate oxide on the substrate;

forming a mask exposing source and drain (S/D) regions of the NVM transistor;

etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and

re-oxidizing the polysilicon gate layer;

depositing a spacer layer over the gates of the NVM transistor and CMOS transistor and the surface of the substrate, and anisotropically dry-etching the spacer layer to form spacers adjacent sidewalls of the gates; and

forming a lightly-doped drain (LDD) mask including openings exposing S/D regions of the NVM transistor and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a LDD adjacent to the gate of the NVM transistor.

20. The method of claim 19 wherein forming the LDD mask further comprises openings exposing S/D regions of the CMOS transistor, and wherein implanting dopants further comprises implanting dopants through these openings exposing S/D regions of the CMOS transistor to concurrently form a LDD adjacent to the gate of the CMOS transistor.