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Methods to integrate SONOS into CMOS flow

  • US 8,916,432 B1
  • Filed: 06/16/2014
  • Issued: 12/23/2014
  • Est. Priority Date: 01/21/2014
  • Status: Active Grant
First Claim
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1. A method comprising:

  • depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a non-volatile memory (NVM) transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer;

    forming a mask exposing source and drain (S/D) regions of the NVM transistor;

    etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and

    implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the NVM transistor.

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