Surface passivation of silicon based wafers

• US 8,916,768 B2
• Filed: 04/12/2006
• Issued: 12/23/2014
• Est. Priority Date: 04/14/2005
• Status: Active Grant

• Current Assignee: Institutt For Energiteknikk, Universitetet I Oslo (Kunnskapsdepartementet), Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Original Assignee: Institutt For Energiteknikk, Universitetet I Oslo (Kunnskapsdepartementet), Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Inventors: Ulyashin, Alexander, Bentzen, Andreas, Svensson, Bengt, Holt, Arve, Sauar, Erik
• Primary Examiner(s): Ayad, Tamir
• Application Number:
  US11/918,325
• Publication Number:
  US 20090056800A1
• Time in Patent Office: 3,177 Days
• Field of Search: 136/256, 438/763, 257/640, 257/E31.119, 257/E21.24, 257/E23.002
• US Class Current: 136/256
• CPC Class Codes: H01L 31/02167 for solar cells
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1864 Annealing
• CPC Class Codes: H01L 31/1868 Passivation
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.

Claims

1. A method for surface passivation of silicon based semiconductors, wherein the method comprises:

cleaning the surface of the semiconductor that is to be passivated,

removing an oxide layer on the surface of the semiconductor that is to be passivated,

introducing the cleaned surface of the semiconductor into a plasma enhanced chemical vapor deposition chamber,

depositing a 10-100 nm thick amorphous silicon passivation layer directly on the surface of the semiconductor that is to be passivated by use of SiH₄ as a precursor gas at about 250°

C.,

depositing a 70-100 nm thick silicon nitride passivation layer on top of the deposited amorphous silicon passivation layer by use of a mixture of SiH₄ and NH₃ as precursor gases at about 250°

C., and finally

annealing the wafer with the deposited passivation layers at a temperature of about 500°

C. for four minutes.

2. The method according to claim 1, wherein

the cleaning of the surface of the semiconductor is obtained by immersion in a H₂SO₄:

H₂O₂ solution, and

the removal of the oxide layer is obtained by immersion in diluted HF.

3. The method according to claim 1, wherein

the precursor gases used for plasma enhanced chemical vapor deposition of either the amorphous silicon layer, the silicon nitride layer, or both layers, also contain hydrogen gas.

4. The method according to claim 1, wherein

the amorphous silicon passivation layer is a silicon carbide film.

5. A surface passivated silicon wafer comprising:

a silicon semiconductor wafer of one type of conductivity (p- or n-type) having at least one thin diffused layer of the other type conductivity (n- or p-type),

a deposited surface passivation dual layer directly on at least a first (light receiving side) surface of the wafer, the deposited surface passivation dual layer being made of a first layer of a 10-100 nm thick amorphous silicon film on the wafer, and a second layer of a 70-100 nm thick silicon nitride film on the first layer, and

wherein the wafer and the deposited dual layer is annealed at a temperature of about 500°

C. for four minutes such that the first surface of the silicon wafer is at least partially saturated by in-diffusion of hydrogen atoms and contains about 10 atom % hydrogen.

6. The surface passivated silicon wafer according to claim 5,

wherein

the first layer is a silicon carbide film.

7. A solar cell comprising:

a silicon semiconductor wafer of one type of conductivity (p- or n-type) having at least one thin diffused layer of the other type conductivity (n- or p-type),

a deposited surface passivation dual layer directly on both a first surface (light receiving side) and a second surface (backside) of the silicon wafer, the deposited surface passivation dual layer being made of a first layer of a 10-100 nm thick amorphous silicon film on the wafer, and a second layer of a 70-100 nm thick silicon nitride film on the first layer,

a current collection grid for the one type of conductivity deposited on top of the surface passivation dual layer on the first surface of the wafer,

a current collection grid for the other type conductivity deposited on top of the surface passivation dual layer on the second surface of the wafer,

soldering pads for interconnection of a plurality of solar cells into a module,

wherein the wafer and the deposited dual layer is annealed at a temperature of about 500°

C. for four minutes such that the first surface of the silicon wafer is at least partially saturated by in-diffusion of hydrogen atoms and contains about 10 atom % hydrogen.

8. The solar cell according to claim 7,

wherein the first layer is a silicon carbide film.

9. A solar cell comprising:

a silicon semiconductor wafer of one type of conductivity (p- or n-type) having at least one thin diffused layer of the other type conductivity (n- or p-type),

a deposited surface passivation dual layer directly on both a first surface (light receiving side) and a second surface (backside) of the silicon wafer, the deposited surface passivation dual layer being made of a first layer of a 10-100 nm thick amorphous silicon film on the wafer, and a second layer of a 70-100 nm thick silicon nitride film on the first layer,

a current collection grid for the one type of conductivity and a current collection grid for the other type conductivity deposited on the second surface of the wafer,

wherein the wafer and the deposited dual layer is annealed at a temperature of about 500°

C. for four minutes such that the first surface of the silicon wafer is at least partially saturated by in-diffusion of hydrogen atoms and contains about 10 atom % hydrogen.

10. The solar cell according to claim 9,

wherein the first layer is a silicon carbide film.