Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls

• US 8,916,912 B2
• Filed: 02/16/2012
• Issued: 12/23/2014
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Tran, Troy
• Application Number:
  US13/398,491
• Publication Number:
  US 20120139039A1
• Time in Patent Office: 1,041 Days
• US Class Current: 257/230
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Claims

1. A semiconductor device comprising:

a transistor comprising a conductive gate within and projecting elevationally outward of a trench in semiconductive material;

a gate dielectric within the trench between the conductive gate and the semiconductive material;

the conductive gate comprising first, second, and third vertically oriented conductive gate sidewalls elevationally outward of the semiconductive material, the first and second vertical gate sidewalls being on the same one of opposing sides of the gate, the second vertical gate sidewall being elevationally outward of the first vertical gate sidewall, the first vertical gate sidewall being laterally outward of the second vertical gate sidewall on the one side of the gate, “

elevationally” and

“

laterally”

being with respect to two different directions that are perpendicular relative to one another, the second vertical gate sidewall overlying the trench laterally between semiconductive material sidewalls of the trench, the third vertical gate sidewall being on the other of the opposing sides of the gate;

a dielectric spacer along the third vertical gate sidewall; and

a dielectric vertical spacing layer having a first portion elevationally between the gate and the semiconductive material on said other of the opposing sides of the gate and a second portion elevationally between the dielectric spacer and the semiconductive material on said other of the opposing sides of the gate, material of the dielectric vertical spacing layer also being on said one side of the gate, the material of the dielectric vertical spacing layer on said one side of the gate being laterally against the first vertical gate sidewall, the material of the dielectric vertical spacing layer on said one side of the gate not being elevationally between the gate and the semiconductive material.

2. The device of claim 1 further comprising a pad dielectric layer having a first portion elevationally between the second portion of the dielectric vertical spacing layer and the semiconductive material.

3. The device of claim 1 wherein the third vertical gate sidewall is laterally outward of the trench on said other of the opposing sides of the gate.

4. An electronic device comprising at least one microprocessor and at least one memory device, wherein the at least one memory device comprises:

at least one transistor comprising;

a conductive gate within and projecting elevationally outward of a trench in semiconductive material;

a gate dielectric within the trench between the conductive gate and the semiconductive material;

the conductive gate comprising first, second, and third vertically oriented conductive gate sidewalls elevationally outward of the semiconductive material, the first and second vertical gate sidewalls being on the same one of opposing sides of the gate, the second vertical gate sidewall being elevationally outward of the first vertical gate sidewall on the one side of the gate, the first vertical gate sidewall being laterally outward of the second vertical gate sidewall, “

elevationally” and

“

laterally”

being with respect to two different directions that are perpendicular relative to one another, the second vertical gate sidewall overlying the trench laterally between semiconductive material sidewalls of the trench, the third vertical gate sidewall being on the other of the opposing sides of the gate;

a dielectric spacer along the third vertical gate sidewall; and

a dielectric vertical spacing layer having a first portion elevationally between the gate and the semiconductive material on said other of the opposing sides of the gate and a second portion elevationally between the dielectric spacer and the semiconductive material on said other of the opposing sides of the gate, material of the dielectric vertical spacing layer also being on said one side of the gate, the material of the dielectric vertical spacing layer on said one side of the gate being laterally against the first vertical gate sidewall, the material of the dielectric vertical spacing layer on said one side of the gate not being elevationally between the gate and the semiconductive material.

5. The device of claim 4 wherein the at least one transistor further comprises a pad dielectric layer having a first portion elevationally between the second portion of the dielectric vertical spacing layer and the semiconductive material.

6. The device of claim 4 wherein the third vertical gate sidewall is laterally outward of the trench on said other of the opposing sides of the gate.