MOSFET having a JFET embedded as a body diode

• US 8,916,929 B2
• Filed: 08/16/2011
• Issued: 12/23/2014
• Est. Priority Date: 06/10/2004
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Li, Jian, Chang, Daniel, Yu, Ho-Yuan
• Primary Examiner(s): Vu, David
• Application Number:
  US13/136,986
• Publication Number:
  US 20110298016A1
• Time in Patent Office: 1,225 Days
• Field of Search: 257/302, 257/328, 257/329, 257/330, 257/E29.118, 438/206, 438/270, 438/212
• US Class Current: 257/330
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.

Claims

1. A trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

a substrate of a first conductivity type;

a first semiconductor layer of the first conductivity type disposed on the substrate, the substrate and the first semiconductor layer comprising a drain of the TMOSFET;

a first plurality of well regions of a second conductivity type disposed in the first semiconductor layer, the second conductivity type being opposite to the first conductivity type;

a second plurality of well regions of the second conductivity type disposed in the first semiconductor layer substantially centered within the first plurality of well regions, the first and second well regions comprising body regions of the TMOSFET and gate regions of a junction field effect transistor (JFET);

a third plurality of well regions of the first conductivity type disposed in the first semiconductor layer substantially centered within the second plurality of well regions, the third well regions comprising source regions of the TMOSFET;

a plurality of trenches disposed in the first semiconductor layer substantially centered within the plurality of first, second and third well regions, the trenches each having vertical walls that extend beneath the first well regions, a dielectric covering the vertical walls;

a second semiconductor layer of the first conductivity type disposed in the plurality of trenches, the second semiconductor layer comprising a trench gate of the TMOSFET; and

a metal layer that electrically couples the first, second and third plurality of well regions and a portion of the first semiconductor layer disposed between the second plurality of well regions, the portion comprising a conducting channel of the JFET, the metal layer comprising a source contact of the TMOSFET and forming a Schottky junction with the conducting channel.

2. The TMOSFET according to claim 1, wherein the first semiconductor layer comprises epitaxial deposited silicon.

3. The TMOSFET according to claim 1, wherein the first well regions comprise a lightly doped portion of the body regions, and the second well regions comprise a heavily doped portion of the body regions.

4. The TMOSFET according to claim 1, wherein a first set of the plurality of trenches are arranged substantially parallel with respect to each other and a second set of the plurality of trenches are arranged normal-to-parallel with respect to the first set of the plurality of trenches.

5. The TMOSFET according to claim 1, wherein the plurality of trenches are arranged substantially parallel with respect to each other.

6. The TMOSFET according to claim 1, wherein the Schottky junction in combination with the JFET form a gated Schottky diode that pinches off the conduction channel during a reverse bias condition.

7. The TMOSFET according to claim 1, wherein the dielectric comprises an oxide layer.

8. The TMOSFET according to claim 1, wherein the second semiconductor layer comprises heavily doped polysilicon.