Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

• US 8,916,937 B1
• Filed: 02/14/2014
• Issued: 12/23/2014
• Est. Priority Date: 07/26/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Hoffmann, Thomas, Ranade, Pushkar, Shifren, Lucian, Thompson, Scott E.
• Primary Examiner(s): Picardat, Kevin M
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US14/180,888
• Time in Patent Office: 312 Days
• Field of Search: 257/E21.633, 257/E21.335, 257/369, 257/192, 257/E21.409, 257/E29.055, 438/199, 438/289, 438/300, 438/514, 438/530
• US Class Current: 257/369
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

Claims

1. A method of forming a first plurality of transistors of a first device type, and a second plurality of transistors of a second device type on a substrate, comprising:

forming a first plurality of wells of a first conductivity type in the substrate;

forming a second plurality of wells of a first conductivity type in the substrate;

doping each of the first plurality of wells to form a corresponding first plurality of screen layers of the first conductivity type, each screen layer of the first plurality of screen layers being disposed closer to a surface of the substrate than the well in which it is formed;

doping each of the second plurality of wells to form a corresponding second plurality of screen layers of the first conductivity type, each screen layer of the second plurality of screen layers being disposed closer to a surface of the substrate than the well in which it is formed;

doping the first plurality of screen layers to introduce a first diffusion-inhibiting dopant species, the first diffusion-inhibiting dopant species being effective to inhibit, but not stop, out-diffusion of dopants from each of the first plurality of screen layers by a first amount;

growing substantially undoped epitaxial layers over the first plurality of screen layers, and over the second plurality of screen layers; and

thermal cycling the substrate;

wherein energy from the thermal cycling drives out-diffusion from each screen layer of the first plurality of screen layers into the corresponding overlying epitaxial layer such that a first range of threshold voltages is obtained in the transistors of the first device type, and drives out-diffusion from each screen layer of the second plurality of screen layers into the corresponding overlying epitaxial layer such that a second range of threshold voltages is obtained in the transistors of the second device type;

wherein doping the first plurality of wells to form the first plurality of screen layers comprises;

implanting at least a first dopant species having a first diffusivity in the first plurality of screen layers, and implanting a second dopant species having a second diffusivity in the second plurality of screen layers;

wherein the first diffusivity is greater than the second diffusivity.

2. The method of claim 1, wherein the each screen layer of the first plurality of screen layers has a doping concentration that is greater than a doping concentration of the first plurality of wells.

3. The method of claim 2, wherein doping the first plurality of screen layers comprises:

implanting one or more dopant species that act as a migration barrier to previously implanted dopant species.

4. The method of claim 2, wherein the first diffusion-inhibiting dopant species comprise carbon.

20. The method of claim 1, wherein the first diffusion-inhibiting dopant species comprises carbon.

5. A method of forming a transistor on a semiconductor substrate, comprising:

performing a first ion implantation to form a doped well in the substrate of a first conductivity type;

performing a second ion implantation to form a doped screen layer in the doped well, the doped screen layer being of the same conductivity type as the first conductivity type;

depositing a semiconductive epitaxial layer over the doped screen layer;

the doped well, screen layer and semiconductive epitaxial layer forming a channel stack;

applying thermal cycling to effect an out-diffusion of dopants from the screen layer into a portion of the semiconductive epitaxial layer, the out-diffusion of dopants producing a first doped region having a first doping profile, a second doped region having a second doping profile, and a third doped region having a third doping profile;

wherein the third doped region is more heavily doped than the second doped region, and the second doped region is more heavily doped than the first doped region.

6. The method of claim 5, further comprising performing a third ion implantation to form a doped anti-punch-through region adjacent the screen layer.

7. The method of claim 5, wherein performing the second ion implantation comprises ion implanting a dopant species comprising at least one of arsenic and antimony.

8. The method of claim 5, wherein performing the second ion implantation comprises ion implanting a dopant species comprising boron.

9. The method of claim 8, further comprising:

performing a third ion implantation of carbon to effect a diffusion-inhibiting layer adjacent the screen layer.

10. The method of claim 9, further comprising:

performing a fourth ion implantation of a material effective to form an amorphization region in the substrate.

11. The method of claim 5, further comprising:

forming a gate structure, a first source/drain structure and a second source/drain structure, configured to apply voltage and conduct electrical current in a portion of the channel.

12. The method of claim 11, further comprising:

performing a halo implantation adjacent the source and drain at selected portions of the screen layers.

13. The method of claim 5, wherein the semiconductive epitaxial layer comprises silicon.

14. The method of claim 13, wherein the semiconductive epitaxial layer further comprises germanium.

15. A method of forming an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) on a semiconductor substrate, comprising:

forming an NFET channel stack by

performing a first ion implantation to form a first doped well of a first conductivity type in the semiconductor substrate,

performing a second ion implantation to form a first doped screen layer in the first doped well, the first doped screen layer being of the first conductivity type,

forming a first silicon epitaxial layer over the first doped screen layer; and

forming a PFET channel stack by

performing a third ion implantation to form a second doped well of a second conductivity type in the semiconductor substrate,

performing a fourth ion implantation to form a second doped screen layer in the second doped well, the second doped screen layer being of the second conductivity type,

forming a second silicon epitaxial layer over the second doped screen layer; and

applying a thermal cycling process to effect an out-diffusion of dopants from the first and second screen layers into a defined portion of the first and second silicon epitaxial layers respectively, the out-diffusion of dopants effective to form a first doped region in the first silicon epitaxial layer and a second doped region in the second silicon epitaxial layer.

16. The method of claim 15, further comprising:

forming a first anti-punch-through region adjacent the first doped screen layer; and

forming a second anti-punch-through region adjacent the second doped screen layer.

17. The method of claim 15, wherein forming the NFET further comprises:

performing a germanium preamorphization ion implantation; and

performing a carbon ion implantation.

18. The method of claim 15, wherein the first and second silicon epitaxial layers comprise a common blanket epitaxial layer.

19. The method of claim 16, wherein forming the first anti-punch-through region comprises performing a fifth ion implantation;

and forming the second anti-punch-through region comprises performing a sixth ion implantation.