Clock data recovery circuit and wireless module including same

• US 8,917,804 B2
• Filed: 02/17/2011
• Issued: 12/23/2014
• Est. Priority Date: 02/17/2011
• Status: Expired due to Fees

• Current Assignee: National University Corporation Hokkaido University
• Original Assignee: National University Corporation Hokkaido University
• Inventors: Sano, Eiichi, Amemiya, Yoshihito
• Primary Examiner(s): Flores, Leon
• Application Number:
  US13/985,949
• Publication Number:
  US 20140003566A1
• Time in Patent Office: 1,405 Days
• Field of Search: 375/238, 375/316, 375/326, 375/364
• US Class Current: 375/364
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/065 and superimposed by modulation

Abstract

A clock data recovery circuit includes a ring oscillator, an oscillation control circuit unit to start or stop the ring oscillator according to existence or absence of a PWM signal, a counter circuit unit to count pulse signals to hold N bits of count value, a register circuit unit which is configured to transmit upper M bits of count value, as a reference count value, in response to a transmission signal, a comparison circuit unit to output a timing clock when the count value exceeds the reference count value, and a transmission control circuit unit to be synchronized with a rising timing of the PWM signal to generate the transmission signal and a reset signal for resetting the counter circuit unit.

Claims

1. A clock data recovery circuit comprising:

an oscillator configured to generate a pulse signal;

a first control circuit unit configured to start and stop an operation of the oscillator according to existence or absence of an input of a Pulse Width Modulation (PWM) signal;

a counter configured to count the pulse signal so as to hold a count value in N number of bit counters, wherein N is an integer greater than 1;

a register including M number of bit registers, wherein M is a natural number smaller than N, the register being configured to transmit upper M bits of the count value held by the N number of bit counters, as a reference count value, in response to input of a transmission signal;

a comparator configured to compare the count value held by the counter with the reference count value held by the register and output a timing clock when the count value exceeds the reference count value; and

a second control circuit unit configured to be synchronized with a rising timing of the PWM signal to generate the transmission signal for transmitting the reference count value from the counter to the register and a reset signal for resetting the counter.

2. The clock data recovery circuit of claim 1, wherein the counter comprises N number of cascade-connected flip-flops as the bit counters;

the register comprises M number of flip-flops as the bit registers; and

outputs of the flip-flops corresponding to the upper M bits among the N number of flip-flops of the counter are connected to inputs of the M number of flip-flops of the register, respectively.

3. The clock data recovery circuit of claim 2, wherein the comparator compares outputs of the flip-flops corresponding to lower M bits of the counter with outputs of the M number of the flip-flops of the register, respectively.

4. A wireless module comprising:

the clock data recovery circuit of claim 1;

an antenna configured to receive the PWM signal; and

an amplifier configured to amplify the PWM signal.