Selectively placing data in thermally constrained memory systems to dynamically adapt to changing environmental conditions

• US 8,918,576 B2
• Filed: 04/24/2012
• Issued: 12/23/2014
• Est. Priority Date: 04/24/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Bert, Luca, Ish, Mark, Rajaram, Rajiv Ganth
• Primary Examiner(s): PEUGH, BRIAN R
• Application Number:
  US13/454,310
• Publication Number:
  US 20130282950A1
• Time in Patent Office: 973 Days
• Field of Search: None
• US Class Current: 711/102
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for selectively placing cache data, comprising the steps of (A) determining a line temperature for a plurality of devices, (B) determining a device temperature for the plurality of devices, (C) calculating an entry temperature for the plurality of devices in response to the cache line temperature and the device temperature and (D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.

Claims

1. A method for selectively placing cache data, comprising the steps of:

(A) determining a line temperature for a plurality of devices;

(B) determining a device temperature for said plurality of devices;

(C) calculating an entry temperature for said plurality of devices in response to said line temperature and said device temperature; and

(D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.

2. The method according to claim 1, wherein said line temperature comprises a cache line temperature, said device temperature comprises a cache device temperature and said entry temperature comprises a cache entry temperature.

3. The method according to claim 2, wherein said cache line temperature comprises a calculation of how often data is written to a particular cache line.

4. The method according to claim 2, wherein said cache device temperature comprises a physical reading of a cache device.

5. The method according to claim 4, wherein said physical reading comprises a temperature reading of said device.

6. The method according to claim 2, wherein said cache device temperature comprises a temperature reading from a plurality of locations of a cache line.

7. The method according to claim 1, wherein step (A) comprises determining a number of times data is written to each of said devices.

8. The method according to claim 1, wherein said plurality of devices each comprise cache memory cells.

9. The method according to claim 1, wherein said plurality of devices are configured as a redundant array of inexpensive disks (RAID).

10. The method according to claim 1, wherein said distribution of said plurality of writes is dynamically adapted in response to changes in said entry temperature.

11. An apparatus comprising:

a processor configured to present/receive data through a bus; and

a memory sub-system configured to read/write data from said processor through said bus, wherein (A) said memory sub-system comprises a plurality of memory elements each configured to present a line temperature reading to said processor, and (B) said processor is configured to (i) determine a device temperature for said plurality of memory elements, (ii) calculate an entry temperature for said plurality of memory elements in response to said line temperature and said device temperature, and (iii) distribute a plurality of write operations across the plurality of memory elements in response to said entry temperature such that thermal energy is distributed evenly over the plurality of memory elements.

12. The apparatus according to claim 11, wherein said plurality of memory elements each comprise a solid state drive.

13. The apparatus according to claim 12, wherein each of said drives comprises a plurality of solid state storage elements.

14. The apparatus according to claim 11, wherein said plurality of memory elements are configured as a redundant array of inexpensive disks (RAID).

15. The apparatus according to claim 11, wherein said distribution of said plurality of writes is dynamically adapted in response to changes in readings of said entry temperature.

16. The apparatus according to claim 11, wherein said line temperature comprises a cache line temperature, said device temperature comprises a cache device temperature and said entry temperature comprises a cache entry temperature.

17. The apparatus according to claim 16, wherein said cache line temperature comprises a calculation of how often data is written to a particular cache line.

18. The apparatus according to claim 16, wherein said cache device temperature comprises a physical temperature reading of a cache device.

19. The apparatus according to claim 16, wherein said cache device temperature comprises a temperature reading from a plurality of locations of one of said memory elements.

20. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory sub-system, wherein said memory sub-system comprises a plurality of memory elements each configured to present a line temperature reading to a bus; and

a control circuit configured to (i) present/receive data through said bus, (ii) determine a device temperature for said plurality of memory elements, (iii) calculate an entry temperature for said plurality of memory elements in response to said line temperature and said device temperature, and (iv) distribute said plurality of read/write operations across said plurality of memory elements in response to said entry temperature such that thermal energy is distributed evenly over said plurality of memory elements.