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Edge-based full chip mask topography modeling

  • US 8,918,743 B1
  • Filed: 08/12/2013
  • Issued: 12/23/2014
  • Est. Priority Date: 08/12/2013
  • Status: Active Grant
First Claim
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1. A computer-implemented method of performing mask topography effect modeling on a mask design layout, the method comprising:

  • applying, using a computing device, a thin mask model to the mask design layout to create a thin mask transmission;

    applying a thick mask model to the mask design layout, the thick mask model comprising a plurality of edge-based kernels;

    applying a rasterization filter to the plurality of edge-based kernels to generate a plurality of filtered kernels, the applying of the thick mask model comprising applying the plurality of filtered kernels to edges in the mask design layout to produce a mask 3D residual; and

    combining the thin mask transmission and the mask 3D residual to create a mask 3D transmission, wherein the mask topography effect modeling on the mask design layout is used to create an improved optical mask for creating an integrated circuit.

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