Methods, systems, and articles of manufacture for implementing physical design decomposition with custom connectivity
First Claim
1. A computer implemented method for implementing physical design decomposition with custom conductivity, comprising:
- at least one processor of a computing system performing a process, the process comprising;
identifying incomplete conductivity information of an electronic design, whereinthe incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design;
partitioning a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and
iteratively moving at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria.
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Accused Products
Abstract
Disclosed are methods, systems, and articles of manufactures for implementing physical design decomposition with custom conductivity by identifying custom, incomplete conductivity for an electronic design, partitioning a physical design space multiple non-overlapping cells, and iteratively moving at least some of the nodes of these multiple cells to generate a floorplan or a placement layout until one or more convergence criteria are satisfied while maintaining the custom, incomplete conductivity. The floorplan or a placement layout generated resembles the final floorplan obtained through a floorplanner or the final placement layout through a placement tool without requiring that complete conductivity information be provided to the floorplanner or placement tool.
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Citations
31 Claims
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1. A computer implemented method for implementing physical design decomposition with custom conductivity, comprising:
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at least one processor of a computing system performing a process, the process comprising; identifying incomplete conductivity information of an electronic design, wherein the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design; partitioning a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and iteratively moving at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An article of manufacture comprising a non-transitory computer readable storage medium storing thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core, causes the at least one processor or the at least one processor core to perform a method for implementing physical design decomposition with custom conductivity, the method comprising:
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at least one processor performing a process, the process comprising; identifying incomplete conductivity information of an electronic design, wherein the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design; partitioning a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and iteratively moving at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria. - View Dependent Claims (21, 22, 23, 24, 25)
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26. A system for using virtual sales process engineering, comprising:
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a computing system that comprises at least one processor having at least one core and is to; identify incomplete conductivity information of an electronic design, wherein the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design; partition a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and iteratively move at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria. - View Dependent Claims (27, 28, 29, 30, 31)
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Specification