Methods, systems, and articles of manufacture for implementing physical design decomposition with custom connectivity

• US 8,918,751 B1
• Filed: 03/15/2013
• Issued: 12/23/2014
• Est. Priority Date: 03/15/2013
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: McCracken, Thaddeus C.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US13/843,706
• Time in Patent Office: 648 Days
• Field of Search: 716/123, 716/124, 716/125
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Disclosed are methods, systems, and articles of manufactures for implementing physical design decomposition with custom conductivity by identifying custom, incomplete conductivity for an electronic design, partitioning a physical design space multiple non-overlapping cells, and iteratively moving at least some of the nodes of these multiple cells to generate a floorplan or a placement layout until one or more convergence criteria are satisfied while maintaining the custom, incomplete conductivity. The floorplan or a placement layout generated resembles the final floorplan obtained through a floorplanner or the final placement layout through a placement tool without requiring that complete conductivity information be provided to the floorplanner or placement tool.

Claims

1. A computer implemented method for implementing physical design decomposition with custom conductivity, comprising:

at least one processor of a computing system performing a process, the process comprising;

identifying incomplete conductivity information of an electronic design, wherein

the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design;

partitioning a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and

iteratively moving at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria.

2. The computer implemented method of claim 1, in which the process further comprises:

inferring conductivity information that is more complete than the incomplete conductivity based at least in part upon the multiple cells.

3. The computer implemented method of claim 1, in which the process further comprises:

reconfiguring the conductivity information by removing connectivity between two nodes of the same number of nodes.

4. The computer implemented method of claim 3, in which the process further comprises:

repartitioning the physical design area based at least in part upon reconfigured conductivity information.

5. The computer implemented method of claim 3, in which the process further comprises:

determining a degree for the same number of nodes;

identifying a cell of the multiple cells that includes a first node and exhibits a first degree higher than the degree;

identifying a number of edges of the cell, wherein the number is equal to the degree; and

removing connectivity between the first node and one or more nodes corresponding to one or more edges of the cell that do not belong to the number of edges identified.

6. The computer implemented method of claim 5, in which the act of identify the number of edges of the cell comprises:

identifying a total number of edges of the cell;

sorting the total number of edges of the cell based at least in part on lengths of the total number of edges; and

selecting a first number of edges from the total number of edges that has been sorted, wherein the first number is equal to the number.

7. The computer implemented method of claim 3, in which the act of reconfiguring the conductivity information is performed to have a substantially uniform distribution of connectivity for a first cell having a first node in an angular direction around the first node.

8. The computer implemented method of claim 1, in which the multiple cells comprise a plurality of Voronoi cells.

9. The computer implemented method of claim 1, wherein no two cells of the multiple cells are overlapping each other.

10. The computer implemented method of claim 1, in which the process further comprises:

anchoring a cell of the multiple cells at an edge of a core area to an input/output cell in an input/output area that substantially surrounds the core area.

11. The computer implemented method of claim 10, in which the act of anchoring the cell is performed using a containment created by the input/output cell.

12. The computer implemented method of claim 11, in which the containment is created by using a force model that cause boundaries of the input/output cell to interact with a input/output node within the input/output cell.

13. The computer implemented method of claim 1, in which the process further comprises:

generating a graph by using the multiple cells as vertices in the graph and at least the conductivity information to create edges between connected vertices.

14. The computer implemented method of claim 1, in which the act of partitioning the physical design area is performed at a higher hierarchical level of the electronic design.

15. The computer implemented method of claim 14, in which the process further comprises:

partitioning the physical design area at a lower hierarchical level into a plurality of cells based at least in part on the multiple cells at the higher hierarchical level of the electronic design.

16. The computer implemented method of claim 15, in which the act of partitioning the physical design area at the lower hierarchical level comprises:

identifying or determining a total number of child nodes at the lower hierarchical level in a parent cell of the multiple cells at the higher hierarchical level;

adding the total number of child nodes to the physical design area; and

determining the plurality of cells based at least in part upon the total number of child nodes.

17. The computer implemented method of claim 16, in which the act of adding the total number of child nodes comprises:

distributing the total number of child nodes based at least in part upon one or more geometric characteristic of the parent cell.

18. The computer implemented method of claim 16, in which the act of partitioning the physical design area at the lower hierarchical level comprises:

deriving or determining one or more models for moving the total number of child nodes at the lower hierarchical level from one or more corresponding models for moving a parent node of the parent cell.

19. The computer implemented method of claim 16, in which the act of partitioning the physical design area at the lower hierarchical level comprises:

reconfiguring the conductivity information at the lower hierarchical level by removing connectivity between two child nodes of the total number of child nodes; and

modifying the plurality of cells at the lower hierarchical level based at least in part upon reconfigured conductivity information at the lower hierarchical level.

20. An article of manufacture comprising a non-transitory computer readable storage medium storing thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core, causes the at least one processor or the at least one processor core to perform a method for implementing physical design decomposition with custom conductivity, the method comprising:

at least one processor performing a process, the process comprising;

identifying incomplete conductivity information of an electronic design, wherein

the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design;

partitioning a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and

iteratively moving at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria.

21. The article of manufacture of claim 20, in which the process further comprises:

inferring conductivity information that is more complete than the incomplete conductivity based at least in part upon the multiple cells;

reconfiguring the conductivity information by removing connectivity between two nodes of the same number of nodes; and

repartitioning the physical design area based at least in part upon reconfigured conductivity information.

22. The article of manufacture of claim 21, in which the process further comprises:

determining a degree for the same number of nodes;

identifying a cell of the multiple cells that includes a first node and exhibits a first degree higher than the degree;

identifying a number of edges of the cell, wherein the number is equal to the degree; and

removing connectivity between the first node and one or more nodes corresponding to one or more edges of the cell that do not belong to the number of edges identified.

23. The article of manufacture of claim 22, in which the act of identify the number of edges of the cell comprises:

identifying a total number of edges of the cell;

sorting the total number of edges of the cell based at least in part on lengths of the total number of edges; and

selecting a first number of edges from the total number of edges that has been sorted, wherein the first number is equal to the number.

24. The article of manufacture of claim 20, in which the process further comprises:

generating a graph by using the multiple cells as vertices in the graph and at least the conductivity information to create edges between connected vertices; and

partitioning the physical design area at a lower hierarchical level into a plurality of cells based at least in part on the multiple cells at a higher hierarchical level of the electronic design, in which the act of partitioning the physical design area is performed at the higher hierarchical level of the electronic design.

25. The article of manufacture of claim 24, in which the act of partitioning the physical design area at the lower hierarchical level comprises:

identifying or determining a total number of child nodes at the lower hierarchical level in a parent cell of the multiple cells at the higher hierarchical level;

adding the total number of child nodes to the physical design area; and

determining the plurality of cells based at least in part upon the total number of child nodes.

26. A system for using virtual sales process engineering, comprising:

a computing system that comprises at least one processor having at least one core and is to;

identify incomplete conductivity information of an electronic design, wherein

the incomplete conductivity information includes no information for connecting at least a part of a first cell in the electronic design with another part of the electronic design;

partition a physical design area into multiple cells having a same number of nodes as a total number of cells in the multiple cells; and

iteratively move at least some of the same number of nodes to generate a floorplan or a placement layout for the electronic design until the multiple cells satisfy one or more criteria.

27. The system of claim 26, in which the computing system is further to:

infer conductivity information that is more complete than the incomplete conductivity based at least in part upon the multiple cells;

reconfigure the conductivity information by removing connectivity between two nodes of the same number of nodes; and

reparation the physical design area based at least in part upon reconfigured conductivity information.

28. The system of claim 27, in which the computing system is further to:

determine a degree for the same number of nodes;

identify a cell of the multiple cells that includes a first node and exhibits a first degree higher than the degree;

identify a number of edges of the cell, wherein the number is equal to the degree; and

remove connectivity between the first node and one or more nodes corresponding to one or more edges of the cell that do not belong to the number of edges identified.

29. The system of claim 28, in which the computing system that is to identify the number of edges of the cell is further to:

identify a total number of edges of the cell;

sort the total number of edges of the cell based at least in part on lengths of the total number of edges; and

select a first number of edges from the total number of edges that has been sorted, wherein the first number is equal to the number.

30. The system of claim 26, in which the computing system is further to:

generate a graph by using the multiple cells as vertices in the graph and at least the conductivity information to create edges between connected vertices; and

partition the physical design area at a lower hierarchical level into a plurality of cells based at least in part on the multiple cells at a higher hierarchical level of the electronic design, in which the act of partitioning the physical design area is performed at the higher hierarchical level of the electronic design.

31. The system of claim 30, in which the computing system that is to partition the physical design area at the lower hierarchical level is further to:

identify or determine a total number of child nodes at the lower hierarchical level in a parent cell of the multiple cells at the higher hierarchical level;

add the total number of child nodes to the physical design area; and

determine the plurality of cells based at least in part upon the total number of child nodes.