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Semiconductor integrated device assembly process

  • US 8,921,164 B2
  • Filed: 02/20/2013
  • Issued: 12/30/2014
  • Est. Priority Date: 02/21/2012
  • Status: Active Grant
First Claim
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1. A process comprising:

  • forming a confinement and spacing structure on a first surface of a first body of semiconductor material, the confinement and spacing structure including a confinement element;

    placing an elastic spacer material on at least a portion of the confinement and spacing structure;

    stacking a second body of semiconductor material over the first body and the elastic spacer material, the stacking causing the elastic spacer material to flow between the first body and the second body while the confinement element confines the flow of the elastic spacer material.

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