Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

• US 8,921,172 B2
• Filed: 04/29/2014
• Issued: 12/30/2014
• Est. Priority Date: 01/03/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Xuefeng, Phelps, Richard A., Rassel, Robert M., Tian, Xiaowei
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US14/264,125
• Publication Number:
  US 20140235021A1
• Time in Patent Office: 245 Days
• Field of Search: 438/186, 438/191, 257/192, 257/256, 257/E21.403, 257/E21.407, 257/E21.421
• US Class Current: 438/191
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Claims

1. A method of forming a junction field effect transistor, said method comprising:

forming, in a semiconductor layer comprising a first semiconductor material, N-type source/drain regions and an N-type channel region, said N-type source/drain regions being adjacent to a first end of said N-type channel region and a second end of said N-type channel region opposite said first end; and

,

forming a first P-type gate adjacent to a first side of said N-type channel region and a second P-type gate adjacent to a second side of said N-type channel region opposite said first gate such that at least one of said first P-type gate and said second P-type gate comprises a second semiconductor material different from said first semiconductor material so as to limit P-type dopant out-diffusion into said N-type channel region.

2. The method of claim 1, said first semiconductor material comprising silicon and said second semiconductor material comprising any of silicon germanium and silicon germanium carbide.

3. The method of claim 1, said first P-type gate and said second P-type gate being formed such that only said first P-type gate comprises said second semiconductor material.

4. The method of claim 1, further comprising providing wafer comprising a substrate, an insulator layer on said substrate and said semiconductor layer on said insulator layer, said semiconductor layer comprising an N-type semiconductor layer and said forming of said N-type source/drain regions comprising forming N-type implant regions in said N-type semiconductor layer such that said N-type implant regions are separated by a designated portion of said N-type semiconductor layer comprising said N-type channel region.

5. The method of claim 4, said forming of said N-type implant regions ensuring that said N-type source/drain regions have a higher concentration of an N-type dopant than said N-type channel region.

6. The method of claim 1, said forming of said first P-type gate and said second P-type gate comprising:

forming, in said semiconductor layer, a first trench positioned laterally adjacent to said first side of said N-type channel region and a second trench positioned laterally adjacent to said second side of said N-type channel region; and

filling said first trench and said second trench with any one of a silicon germanium layer and a silicon germanium carbide layer so as to form said first P-type gate and said second P-type gate, respectively.

7. The method of claim 1, said forming of said first P-type gate and said second P-type gate comprising:

forming, in said semiconductor layer, a trench positioned laterally adjacent to said first side of said N-type channel region;

filling said trench with any one of a silicon germanium layer and a silicon germanium carbide layer to form said first P-type gate; and

,

forming, in said semiconductor layer, a P-type implant region adjacent to said second side of said N-type channel region.

8. A method of forming a junction field effect transistor, said method comprising:

providing a silicon substrate having a top surface;

forming a first N-well in said substrate;

forming a first P-type gate for said junction field effect transistor, said forming of said first P-type gate comprising forming a P-well in said substrate above and abutting said first N-well;

forming an N-type channel region for said junction field effect transistor, said forming of said N-type channel region comprising forming a second N-well in said substrate above and abutting said P-well; and

forming a second P-type gate for said junction field effect transistor, said forming of said second P-type gate comprising;

forming a trench that extends vertically from said top surface of said substrate to said second N-well, said trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate; and

filling said trench with any one of a silicon germanium layer and a silicon germanium carbide layer.

9. The method of claim 8, said filling of said trench comprising performing an epitaxial deposition process.

10. The method of claim 9, said forming of said second P-type gate further comprising any one of in-situ doping and subsequently doping said one of said silicon germanium layer and said silicon germanium carbide layer with a P-type dopant.

11. The method of claim 8, said first N-well, said P-well and said second N-well being formed using ion implantation processes with different ion implantation energies so that said P-well is above said first N-well and said second N-well is above said P-well.

12. The method of claim 8, further comprising,

forming N-type source/drain regions for said junction field effect transistor, said forming of said N-type source/drain regions comprising forming N-type implant regions at said top surface of said substrate, said N-type implant regions being formed so as to abut said N-type channel region, so as to have a higher concentration of an N-type dopant than said N-type channel region and so that said second P-type gate is positioned laterally between said N-type implant regions;

and

forming isolation structures so that said N-type source/drain regions are isolated from said second P-type gate.

13. The method of claim 8, further comprising:

forming a first contact extending vertically from said top surface to said first P-type gate; and

forming a second contact extending vertically from said top surface to said first N-well.

14. The method of claim 13, said first contact being formed so as to be electrically connected to said second P-type gate.

15. A method of forming a junction field effect transistor, said method comprising:

comprising;

providing a silicon substrate having a top surface;

forming an N-well in said substrate below said top surface;

forming a first trench that extends vertically from said top surface into said N-well;

forming a first P-type gate for said junction field effect transistor, said forming of said first P-type gate comprising forming any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer in a lower portion of said first trench;

forming an N-type channel region for said junction field effect transistor, said forming of said N-type channel region comprising forming an N-type silicon layer in said first trench on said first P-type gate; and

forming a second P-type gate for said junction filed effect transistor, said forming of said P-type gate comprising;

forming a second trench extending vertically to said N-type silicon layer, said second trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate; and

filling said second trench with a semiconductor layer.

16. The method of claim 15, said filling of said second trench comprising filling said second trench with any one of a silicon layer, a second silicon germanium layer and a second silicon germanium carbide layer.

17. The method of claim 15, said filling of said second trench comprising filling said second trench with any one of a silicon layer, a second silicon germanium layer and a second silicon germanium carbide layer.

18. The method of claim 15, further comprising:

forming N-type source/drain regions for said junction field effect transistor, said forming of said N-type source/drain regions comprising forming N-type implant regions at said top surface of said substrate, said N-type implant regions being formed so as to abut said N-type channel region, so as to have a higher concentration of an N-type dopant than said N-type channel region and so that said second P-type gate is positioned laterally between said N-type implant regions; and

forming isolation structures so that said N-type source/drain regions are isolated from said second P-type gate.

19. The method of claim 15, further comprising:

forming a first contact extending vertically from said top surface to said first P-type gate; and

forming a second contact extending vertically from said top surface to said N-well.

20. The method of claim 19, said first contact being formed so as to be electrically connected to said second P-type gate.