Pre-gate dielectric process using hydrogen annealing

• US 8,921,193 B2
• Filed: 01/17/2006
• Issued: 12/30/2014
• Est. Priority Date: 01/17/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chi-Chun, Chen, Shih-Chang, Teo, Jocelyn Wei-Yee
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US11/333,399
• Publication Number:
  US 20070166904A1
• Time in Patent Office: 3,269 Days
• Field of Search: 438/308, 438/795
• US Class Current: 438/308
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming trench isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the trench isolation regions define a first active region and a second active region;

forming a first gate dielectric over the semiconductor substrate in the first active region;

forming a convex surface of the top surface of the semiconductor substrate in the second active region by performing a hydrogen anneal on the semiconductor substrate in an ambient containing hydrogen while the top surface of the semiconductor substrate in the second active region is exposed, the convex surface being between a first source/drain region of the second active region and a second source/drain region of the second active region, a curvature of the convex surface being convex in a direction from the first source/drain region to the second source/drain region; and

forming a second gate dielectric over the convex surface in the second active region.

2. The method of claim 1, wherein the ambient contains substantially pure hydrogen.

3. The method of claim 1, wherein the hydrogen anneal is performed at a temperature of higher than about 900 degrees Celsius.

4. The method of claim 1, wherein the hydrogen anneal is performed at a hydrogen pressure of less than about 20 Torr.

5. The method of claim 1, wherein, after the hydrogen anneal, the top surface of the semiconductor substrate in the second active region has a center portion higher than an edge portion.

6. The method of claim 1, wherein the hydrogen anneal is performed between the forming the first gate dielectric and forming a gate electrode in the first active region.

7. The method of claim 1, wherein the hydrogen anneal is performed after forming a first gate electrode in the first active region.

8. The method of claim 1 further comprising the steps of:

forming a first gate electrode on the first gate dielectric;

forming a first spacer on a sidewall of the first gate electrode;

forming a third source/drain region and a fourth source/drain region on opposite sides of the first gate dielectric;

forming a second gate electrode on the second gate dielectric;

forming a second spacer on a sidewall of the second gate electrode; and

forming the first source/drain region and the second source/drain region on opposite sides of the second gate dielectric.

9. The method of claim 8, wherein the first spacer and the second spacer are formed simultaneously.

10. The method of claim 8, wherein the first source/drain region, the second source/drain region, the third source/drain region, and the fourth source/drain region are formed simultaneously.

11. The method of claim 8, wherein the convex surface comprises an entirety of the top surface of the semiconductor substrate in the second active region between the first source/drain region and the second source/drain region.

12. The method of claim 1 further comprising performing a cleaning step to clean exposed portions of the semiconductor substrate after the forming the first gate dielectric and before the performing the hydrogen anneal.

13. The method of claim 1, wherein after the performing the hydrogen anneal, the convex surface of the top surface of the semiconductor substrate in the second active region increases in height from the first source/drain region to a portion of the semiconductor substrate underlying the second gate dielectric in the direction from the first source/drain region to the second source/drain region substantially monotonically and continuously.

14. The method of claim 1, wherein the curvature of the convex surface introduces a strain on the top surface of the semiconductor substrate in the second active region.

15. A method of forming a semiconductor structure, the method comprising:

forming trench isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the trench isolation regions define a first active region and a second active region;

after forming the trench isolation regions, forming a first gate dielectric over the semiconductor substrate in the first active region;

forming a first gate electrode over the first gate dielectric;

after the steps of forming the first gate dielectric and the first gate electrode, performing a hydrogen anneal on the semiconductor substrate in an ambient containing substantially pure hydrogen, wherein the top surface of the semiconductor substrate in the second active region forms a round surface having a curvature that extends from one trench isolation region across the entire second active region to another trench isolation region;

after the step of performing the hydrogen anneal, forming a second gate dielectric over the round surface of the semiconductor substrate in the second active region such that the second gate dielectric is non-planar; and

forming a second gate electrode over the second gate dielectric.

16. The method of claim 15, further comprising:

forming a first source region and a first drain region on opposite sides of the first gate dielectric; and

forming a second source region and a second drain region on opposite sides of the second gate dielectric.

17. The method of claim 16, wherein, after the step of performing the hydrogen anneal and the step of forming the second source region and the second drain region, a portion of the top surface of the semiconductor substrate in the second active region between the second source region and the second drain region has a convex surface.

18. The method of claim 16, wherein the hydrogen anneal is performed before the forming the second source region and the second drain region.

19. The method of claim 15 further comprising performing a cleaning step to clean exposed portions of the semiconductor substrate after the step of forming the first gate dielectric and before the step of performing the hydrogen anneal.

20. The method of claim 15, wherein after the step of performing the hydrogen anneal, the round surface of the second active region increases in height from portions closer to the trench isolation regions to portions closer to a center of the second active region substantially monotonically and continuously.

21. A method of forming a semiconductor structure, the method comprising:

forming trench isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the trench isolation regions define a first active region and a second active region;

forming a first gate dielectric over the semiconductor substrate in the first active region;

after forming the first gate dielectric, performing a hydrogen anneal on the semiconductor substrate in an ambient containing hydrogen while the top surface of the semiconductor substrate in the second active region is exposed, the hydrogen anneal rounding the top surface of the semiconductor substrate in the second active region between a first source/drain region of the second active region and a second source/drain region of the second active region, the rounding of the top surface of the semiconductor substrate in the second active region forming an arc of the top surface of the semiconductor substrate in a direction from the first source/drain region to the second source/drain region; and

after performing the hydrogen anneal, forming a second gate dielectric over the top surface of the semiconductor substrate in the second active region, the second gate dielectric being disposed between the first source/drain region and the second source/drain region.