Semiconductor constructions, DRAM arrays, and methods of forming semiconductor constructions

• US 8,921,909 B2
• Filed: 04/16/2014
• Issued: 12/30/2014
• Est. Priority Date: 05/17/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fischer, Mark
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US14/254,720
• Publication Number:
  US 20140225175A1
• Time in Patent Office: 258 Days
• Field of Search: 257/68, 257/71, 257296-313, 257905-908, 257E27084-E27096, 257/E21.646, 365/222
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

Claims

1. A DRAM array, comprising:

a plurality of transistors supported by a base;

each transistor comprising a gate;

a channel proximate the gate; and

a pair of source/drain regions on opposing sides of the channel;

each transistor comprising a dielectric material between the gate and the channel;

capacitors electrically coupled with source/drain regions of the transistors;

wherein each channel has a longitudinal axis from one of the source/drain regions to the other, and has a lateral periphery along a cross-section substantially orthogonal to the longitudinal axis;

wherein the lateral periphery is a shape having a bottom surface, a top surface, and a pair of side surfaces extending from the bottom surface to the top surface;

wherein the dielectric material of each transistor is along and directly against entireties of the top and side surfaces of the shape of the lateral periphery of the channel, and extends under an entirety of the bottom surface but is only directly against a portion of the bottom surface;

the dielectric material from one side of the shape contacting the dielectric material from the other side of the shape under the bottom surface; and

wherein the gate of each transistor extends conformally along the dielectric material along the top and side surfaces of the shape of the lateral periphery of the channel, and extends under the channel.

2. The DRAM array of claim 1 wherein the base comprises monocrystalline silicon.

3. The DRAM array of claim 1 wherein the dielectric material comprises silicon dioxide.

4. The DRAM array of claim 1 wherein the gate comprises metal.

5. A DRAM array, comprising:

a plurality of transistors supported by a base;

each transistor comprising a gate formed with gate material;

a channel proximate the gate; and

a pair of source/drain regions on opposing sides of the channel;

each transistor comprising a dielectric material between the gate material and the channel;

wherein each channel has a longitudinal axis from one of the source/drain regions to the other, and has a lateral periphery along a cross-section substantially orthogonal to the longitudinal axis;

wherein the dielectric material of each transistor is conformally along and directly against top and side surfaces of the lateral periphery of the channel, and extends under an entirety of a bottom surface of the lateral periphery of the channel but is only directly against a portion of the bottom surface;

dielectric material from one side of the channel contacting dielectric material from the other side of the channel under the bottom surface; and

wherein the gate material of each transistor gate extends conformally along the dielectric material along the top and side surfaces of the lateral periphery of the channel.

6. A DRAM array, comprising:

at least one transistor comprising a gate;

a channel proximate the gate; and

a pair of source/drain regions on opposing sides of the channel;

the source/drain regions and channel together forming a segment that extends primarily horizontally;

the transistor comprising a dielectric material between the gate and the channel;

the channel having a longitudinal axis from one of the source/drain regions to the other, and having a lateral periphery along a cross-section substantially orthogonal to the longitudinal axis;

the dielectric material being along and directly against top and side surfaces of the lateral periphery of the channel, and extending under an entirety of the bottom surface, but being only directly against a portion of the bottom surface;

the dielectric material from one side of the lateral periphery contacting the dielectric material from the other side of the lateral periphery under the bottom surface; and

the gate being comprised by gate material that wraps substantially entirely around the lateral periphery of the channel.

7. The DRAM array of claim 6 wherein the gate material comprises metal.

8. The DRAM array of claim 6 wherein the lateral periphery is a four-sided polygon.