Devices with nanocrystals and methods of formation
First Claim
1. An electronic device comprising:
- a substrate having a pair of diffused regions with a diffusion type opposite that of the substrate;
a plurality of dielectric layers disposed over the substrate, the plurality of dielectric layers comprising ion nucleation sites embedded in a surface of the plurality of dielectric layers;
a plurality of layers of electrically isolated nanocrystals disposed upon the plurality of dielectric layers, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals, each layer of the plurality of layers of electrically isolated nanocrystals vertically spaced from the other layers of electrically isolated nanocrystals; and
a control gate disposed above the plurality of dielectric layers.
8 Assignments
0 Petitions
Accused Products
Abstract
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.
-
Citations
40 Claims
-
1. An electronic device comprising:
-
a substrate having a pair of diffused regions with a diffusion type opposite that of the substrate; a plurality of dielectric layers disposed over the substrate, the plurality of dielectric layers comprising ion nucleation sites embedded in a surface of the plurality of dielectric layers; a plurality of layers of electrically isolated nanocrystals disposed upon the plurality of dielectric layers, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals, each layer of the plurality of layers of electrically isolated nanocrystals vertically spaced from the other layers of electrically isolated nanocrystals; and a control gate disposed above the plurality of dielectric layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A system comprising:
-
a controller; and an electronic device coupled to the controller, the electronic device comprising a plurality of floating gate transistors, each floating gate transistor comprising; a source and a drain formed in a substrate and separated laterally from each other by a region; a plurality of gate dielectrics disposed above the substrate; a plurality of layers of isolated nucleation sites, each layer disposed in different gate dielectrics; a plurality of layers of electrically isolated nanocrystals, each layer disposed on a top surface of the different gate dielectrics with a substantially even statistical distribution above and across the region, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals; an inter-gate dielectric disposed over the plurality of gate dielectrics; and forming a control gate electrode disposed over the inter-gate dielectric. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A memory cell comprising:
-
a channel region; a first dielectric material adjacent to the channel region; a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures; a second dielectric material adjacent to the plurality of nanoscale structures; and a control gate adjacent to the second dielectric material. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
-
-
39. A transistor comprising:
-
a channel region; first dielectric material adjacent to the channel region; a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures; second dielectric material adjacent to the plurality of nanoscale structures; and a control gate adjacent to the second dielectric.
-
-
40. A memory device comprising a plurality of memory cells, wherein each of the memory cells comprises:
-
a channel region; first dielectric material adjacent to the channel region; a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures; second dielectric material adjacent to the plurality of nanoscale structures; and a control gate adjacent to the second dielectric.
-
Specification