Semiconductor device

• US 8,921,920 B2
• Filed: 03/13/2012
• Issued: 12/30/2014
• Est. Priority Date: 06/23/2011
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawanaka, Shigeru, Tatsumura, Kosuke, Yasuda, Naoki, Fujiki, Jun, Kawasumi, Atsushi
• Primary Examiner(s): Fulk, Steven J
• Application Number:
  US13/418,620
• Publication Number:
  US 20120326224A1
• Time in Patent Office: 1,022 Days
• Field of Search: 257/324, 257/E29.309
• US Class Current: 257/324
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate; and

a semiconductor element configured to comprise an FET which is formed on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state,

wherein the semiconductor element comprises;

an insulating film disposed above a part where a channel of the semiconductor substrate is formed;

a gate electrode disposed above the insulating film; and

a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel,

wherein when the semiconductor element is an n-type FET, the charge trap film sets the threshold voltage to a first voltage level when the semiconductor element is in the OFF state by capturing electrons from the gate electrode and becoming a neutral state, and sets the threshold voltage to a second voltage level lower than the first voltage level when the semiconductor element is in the ON state by transferring electrons to the gate electrode, and

when the semiconductor element is a p-type FET, the charge trap film sets an absolute value of the threshold voltage to a third voltage level when the semiconductor element is in the OFF state by transferring extra electrons to the gate electrode and becoming the neutral state, and sets the absolute value of the threshold voltage to a fourth voltage level lower than the third voltage level when the semiconductor element is in the ON state by capturing electrons from the gate electrode.

2. The semiconductor device of claim 1,

wherein the charge trap film is an SiNx film, the x representing a mole ratio of N to Si and comprising a value within a range of 0.67<

x<

1.33,

the charge trap film comprises a film thickness Tct comprising a value within a range of 0.34 nm<

Tct<

7 nm,

the insulating film is an SION film in which a mole ratio of N to a sum of Si, O, and N expressed as {N/(Si+O+N)} is a value within a range of 0≦

{N/(Si+O+N)}<

0.35, and

the insulating film has a film thickness Tox comprising a value within a range of 0.64 nm<

Tox.

3. The semiconductor device of claim 1,

wherein the insulating film comprises a film thickness Tox comprising a value within a range of 0.64 nm<

Tox<

2.70 nm.

4. The semiconductor device of claim 1,

wherein the gate electrode is an n-type polysilicon film when the semiconductor element is n-type, and is a p-type polysilicon film when the semiconductor element is p-type.

5. The semiconductor device of claim 1,

wherein the gate electrode and the charge trap film are in contact with each other, and

an interface of the gate electrode in contact with the charge trap film comprises a material including at least one of TaC, TaN, TiN, TiCN, TiAlN, W, WN, and Mo.

6. The semiconductor device of claim 1, further comprising:

a first n-type FET and a first p-type FET connected in series between a first power-supply line and a second power-supply line;

a second n-type FET and a second p-type FET connected in series between the first power-supply line and the second power-supply line;

a first junction disposed between the first n-type FET and the first p-type FET;

a second junction disposed between the second n-type FET and the second p-type FET;

a first data node connected to a gate of the second n-type FET, a gate of the second p-type FET, and the first junction;

a second data node connected to a gate of the first n-type FET, a gate of the first p-type FET, and the second junction;

a third n-type FET connected between the first data node and a first data line; and

a fourth n-type FET connected between the second data node and a second data line,

wherein each of the first n-type FET and the second n-type FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film in each of the first n-type FET and the second n-type FET are same as the semiconductor element in material, composition range, and film thickness range.

7. The semiconductor device of claim 6,

wherein the charge trap film in each of the first n-type FET and the second n-type FET comprises a film thickness Tct having a value within a range of 0.45 nm<

Tct<

2.45 nm, and

the insulating film is an SiON film in which a mole ratio of N to a sum of Si, O, and N expressed as {N/(Si+O+N)} is a value within a range of 0≦

{N/(Si+O+N)}<

0.35, and

the insulating film comprises a film thickness Tox having a value within a range of 0.64 nm<

Tox<

2.70 nm.

8. The semiconductor device of claim 7,

wherein the film thickness Tct of the charge trap film comprises a value within a range of 0.72 nm<

Tct<

2.00 nm.

9. The semiconductor device of claim 7,

wherein the film thickness Tox of the insulating film comprises a value within a range of 0.87 nm<

Tox<

2.70 nm.

10. The semiconductor device of claim 9,

wherein the film thickness Tox of the insulating film comprises a value within a range of 1.09 nm<

Tox<

2.70 nm.

11. The semiconductor device of claim 6,

wherein each of the third n-type FET and the fourth n-type FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film in each of the third n-type FET and the fourth n-type FET are same as the semiconductor element in material, composition range, and film thickness range.

12. The semiconductor device of claim 6,

wherein each of the first p-type FET and the second p-type FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film in each of the first p-type FET and the second p-type FET are same as the semiconductor element in material, composition range, and film thickness range.

13. The semiconductor device of claim 6,

wherein each of the first and second n-type FETs comprises a substrate potential set to a ground potential, and each of the first and second p-type FETs comprises a substrate potential set to a power-supply potential.

14. The semiconductor device of claim 1, further comprising:

a first n-type FET and a first p-type FET connected in series between a first power-supply line and a second power-supply line;

a second n-type FET and a second p-type FET connected in series between the first power-supply line and the second power-supply line;

a first junction disposed between the first n-type FET and the first p-type FET;

a second junction disposed between the second n-type FET and the second p-type FET;

a first data node connected to a gate of the second n-type FET, a gate of the second p-type FET, and the first junction;

a second data node connected to a gate of the first n-type FET, a gate of the first p-type FET, and the second junction;

a third n-type FET connected between the first data node and a first data line; and

a fourth n-type FET connected between the second data node and a second data line; and

a fifth n-type FET configured to comprise a gate connected to the first data node,

wherein the fifth n-type FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film of the fifth n-type FET are same as the semiconductor element in material, composition range, and film thickness range.

15. The semiconductor device of claim 1, further comprising:

a first nonvolatile FET and a second nonvolatile FET connected in series between a first data line and a second data line, each of the FETs being capable of nonvolatilely storing a data bit supplied from its corresponding data line;

a junction disposed between the first nonvolatile FET and the second nonvolatile FET; and

a switch FET configured to comprise a gate connected to the junction, and to be turned on or off depending on the data stored in the first and second nonvolatile FETs,

wherein the switch FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film of the switch FET are same as the semiconductor element in material, composition range, and film thickness range.

16. The semiconductor device of claim 1, further comprising:

a logic circuit block configured to comprise a plurality of FETs;

a virtual power-supply line connected to a reference power-supply terminal of the logic circuit block; and

a power switch FET configured to switch whether or not the virtual power-supply line should be set to a predetermined reference voltage,

wherein the power switch FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film of the power switch FET are same as the semiconductor element in material, composition range, and film thickness range.

17. A semiconductor device, comprising:

a semiconductor substrate; and

a semiconductor element configured to be formed of an FET which is formed on the semiconductor substrate and changes a threshold voltage depending on an OFF state and an ON state,

the semiconductor element includes;

an insulating film configured to be formed on the semiconductor substrate;

a charge trap film configured to be formed on the insulating film; and

a gate electrode configured to be arranged to be in contact with the charge trap film,

wherein the charge trap film is an SiNx film, the x representing a mole ratio of N to Si and having a value within a range of 0.67<

x<

1.33,

the charge trap film comprises a film thickness Tct having a value within a range of 0.34 nm<

Tct<

7 nm,

the insulating film is an SiON film in which a mole ratio of N to a sum of Si, O, and N expressed as {N/(Si+O+N)} is a value within a range of 0≦

{N/(Si+O+N)}<

0.35, and

the insulating film comprises a film thickness Tox comprising a value within a range of 0.64 nm<

Tox,

wherein when the semiconductor element is an n-type FET, the charge trap film sets the threshold voltage to a first voltage level when the semiconductor element is in the OFF state by capturing electrons from the gate electrode and becoming a neutral state, and sets the threshold voltage to a second voltage level lower than the first voltage level when the semiconductor element is in the ON state by transferring electrons to the gate electrode, and

when the semiconductor element is a p-type FET, the charge trap film sets an absolute value of the threshold voltage to a third voltage level when the semiconductor element is in the OFF state by transferring extra electrons to the gate electrode and becoming the neutral state, and sets the absolute value of the threshold voltage to a fourth voltage level lower than the third voltage level when the semiconductor element is in the ON state by capturing electrons from the gate electrode.

18. The semiconductor device of claim 17, further comprising:

a first n-type FET and a first p-type FET connected in series between a first power-supply line and a second power-supply line;

a second n-type FET and a second p-type FET connected in series between the first power-supply line and the second power-supply line;

a first junction disposed between the first n-type FET and the first p-type FET;

a second junction disposed between the second n-type FET and the second p-type FET;

a first data node connected to a gate of the second n-type FET, a gate of the second p-type FET, and the first junction;

a second data node connected to a gate of the first n-type FET, a gate of the first p-type FET, and the second junction;

a third n-type FET connected between the first data node and a first data line; and

a fourth n-type FET connected between the second data node and a second data line,

wherein each of the first n-type FET and the second n-type FET comprises a layer structure same as the semiconductor element, and the charge trap film and the insulating film in each of the first n-type FET and the second n-type FET are same as the semiconductor element in material, composition range, and film thickness range.