Semiconductor device

• US 8,921,944 B2
• Filed: 07/19/2011
• Issued: 12/30/2014
• Est. Priority Date: 07/19/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wu, Chun-Yuan, Liu, Chih-Chien
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Oh, Jaehwan
• Application Number:
  US13/185,517
• Publication Number:
  US 20130020648A1
• Time in Patent Office: 1,260 Days
• Field of Search: 257/192, 257/506, 257/510
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.

Claims

1. A semiconductor device, comprising:

a substrate;

at least two metal-oxide semiconductor (MOS) transistors disposed in the substrate, wherein the MOS transistor comprises a gate structure and a source/drain disposed in the substrate adjacent to two sides of the gate structure;

at least one stress plug disposed between two MOS transistors, and the stress plug is not electrically connected to the source/drain;

a shallow trench isolation (STI) disposed in the substrate and between two MOS transistors, wherein the STI comprises a stress material, and the MOS transistors adjacent to two sides of the STI are transistors of the same conductivity type; and

at least one conductive plug disposed on the substrate to connect the source/drain, wherein the stress plug surrounds and extends parallel to the gate structure, but not in direct contact with the gate structure, and the conductive plug is disposed between the gate structure and the stress plug.

2. The semiconductor device of claim 1, wherein the stress material is selected from a material consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxynitride.

3. The semiconductor device of claim 2, wherein the stress of silicon nitride is between −

3.5 GPa to 2.0 GPa.

4. The semiconductor device of claim 2, wherein the stress of boron nitride is between −

1 GPa to −

2 GPa.

5. The semiconductor device of claim 1, wherein the MOS transistor further comprises:

a spacer disposed around the gate structure.

6. The semiconductor device of claim 1, further comprising a stress layer disposed in the substrate and surface of the gate structure.

7. The semiconductor device of claim 5, wherein the gate structure comprises a metal gate or a polysilicon gate.

8. A semiconductor device, comprising:

a substrate;

at least two metal-oxide semiconductor (MOS) transistors disposed in the substrate, wherein the MOS transistor comprises a gate structure and a source/drain disposed in the substrate adjacent to two sides of the gate structure;

a dielectric layer disposed on the substrate to cover the MOS transistor;

at least one stress plug disposed in the dielectric layer and between two MOS transistors, wherein the stress plug comprises a stress material, and the MOS transistors adjacent to two sides of the stress plugs are transistors of the same conductivity type, the stress plug is not electrically connected to the source/drain of the MOS transistor, the top surface of the stress plug is substantially even to the top surface of dielectric layer and also higher than the MOS transistor; and

at least one conductive plug disposed on the substrate to connect the source/drain, wherein the stress plug surrounds and extends parallel to a gate structure, but not in direct contact with the gate structure, and the conductive plug is disposed between the gate structure and the stress plug.

9. The semiconductor device of claim 8, wherein the stress material is selected from a material consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxynitride.

10. The semiconductor device of claim 9, wherein the stress of silicon nitride is between −

3.5 GPa to 2.0 GPa.

11. The semiconductor device of claim 9, wherein the stress of boron nitride is between −

1 GPa to −

2 GPa.

12. The semiconductor device of claim 8, wherein the MOS transistor further comprises:

a spacer disposed around the gate structure.

13. The semiconductor device of claim 12, further comprising a stress layer disposed in the substrate and surface of the gate structure.

14. The semiconductor device of claim 12, wherein the gate structure comprises a metal gate or a polysilicon gate.

15. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming at least two metal-oxide semiconductor (MOS) transistors in the substrate, wherein the MOS transistor comprises a gate structure and a source/drain disposed in the substrate adjacent to two sides of the gate structure;

forming a dielectric layer on the substrate to cover the MOS transistor;

forming at least a contact hole in the dielectric layer and between two MOS transistors;

filling the contact hole with a stress material to form at least one stress plug, wherein the MOS transistors adjacent to two sides of the stress plugs are transistors of the same conductivity type, and the stress plug is not electrically connected to the source/drain of the MOS transistor, the top surface of the stress plug is substantially even to the top surface of dielectric layer and also higher than the MOS transistor; and

forming at least one conductive plug on the substrate to connect the source/drain, wherein the stress plug surrounds and extends parallel to a gate structure, but not in direct contact with the gate structure, and the conductive plug is disposed between the gate structure and the stress plug.

16. The method of claim 15, wherein the stress material is selected from a material consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxynitride.

17. The method of claim 16, wherein the stress of silicon nitride is between −

3.5 GPa to 2.0 GPa.

18. The method of claim 16, wherein the stress of boron nitride is between −

1 GPa to −

2 GPa.

19. The method of claim 15, wherein the MOS transistor further comprises:

a spacer disposed around the gate structure.

20. The method of claim 19, further comprising a stress layer disposed in the substrate and surface of the gate structure.

21. The method of claim 19, wherein the gate structure comprises a metal gate or a polysilicon gate.