Semiconductor device and structure

• US 8,921,970 B1
• Filed: 03/05/2014
• Issued: 12/30/2014
• Est. Priority Date: 12/22/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Le, Thao P
• Application Number:
  US14/198,041
• Time in Patent Office: 300 Days
• Field of Search: 257/499, 257/E23.145, 257/774, 438/598, 438/618
• US Class Current: 257/499
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01104 Refractory metals
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; where the second layer includes a through layer via with a diameter of less than 150 nm, and where at least one of the second transistors includes a back-bias structure.

Claims

1. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,

wherein said second layer comprises a through layer via with a diameter of less than 150 nm, and

wherein at least one of said second transistors comprise a back-bias structure.

2. An Integrated Circuit device according to claim 1,

wherein said back-bias structure comprises a conductive layer strip, said conductive layer strip controlled by at least one of said plurality of second transistors.

3. An Integrated Circuit device according to claim 1, further comprising:

at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.

4. An Integrated Circuit device according to claim 1, further comprising:

a shielding layer,

wherein said shielding layer provides shielding for said at least one metal layer from heat resulting from optical annealing of said second transistors.

5. An Integrated Circuit device according to claim 1,

wherein said back-bias structure comprises a refractory metal.

6. An Integrated Circuit device according to claim 1, further comprising:

a conductive layer underneath said second layer,

wherein said conductive layer provides power to at least one of said second transistors.

7. An Integrated Circuit device according to claim 1, further comprising:

a conductive pad overlying at least one of said second transistors.

8. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,

wherein said second layer comprises a through layer via with a diameter of less than 150 nm; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said second transistors.

9. An Integrated Circuit device according to claim 8,

wherein at least one of said second transistors comprises a back-bias structure.

10. An Integrated Circuit device according to claim 8, further comprising:

at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.

11. An Integrated Circuit device according to claim 8, further comprising:

a shielding layer,

wherein said shielding layer provides shielding for said at least one metal layer from heat resulting from optical annealing of said second transistors.

12. An Integrated Circuit device according to claim 8,

wherein said at least one conductive structure is disposed between said base wafer and said second layer.

13. An Integrated Circuit device according to claim 8, further comprising:

a conductive pad overlying at least one of said second transistors.

14. An Integrated Circuit device according to claim 8, further comprising:

an I/O circuit, said I/O circuit design is adapted to interface with external devices,

wherein said I/O circuit comprises at least one of said second transistors.

15. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,

wherein said plurality of second transistors comprise single crystal, and

wherein said second layer comprises a through layer via with a diameter of less than 150 nm;

a plurality of conductive pads,

wherein at least one of said conductive pads overlays at least one of said second transistors; and

at least one I/O circuit,

wherein said at least one I/O circuit is adapted to interface with external devices through at least one of said plurality of conductive pads,

wherein said at least one I/O circuit comprises at least one of said second transistors.

16. An Integrated Circuit device according to claim 15,

wherein at least one of said second transistors comprise a back-bias structure.

17. An Integrated Circuit device according to claim 15, further comprising:

at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.

18. An Integrated Circuit device according to claim 15, further comprising:

a shielding layer,

wherein said shielding layer provides shielding for said at least one metal layer from heat resulting from optical annealing of said second transistors.

19. An Integrated Circuit device according to claim 15, further comprising:

at least one conductive layer underneath said second layer,

wherein said at least one conductive layer comprises a refractory metal.

20. An Integrated Circuit device according to claim 15, further comprising:

at least one conductive structure,

wherein said at least one conductive provides power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said second transistors.